Comparison of Different SRAM Cell Topologies Using 180 nm Technology

  • D. ChaudhuriEmail author
  • Kousik Roy
  • A. Nag
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 41)


With an overview and the limitations of the conventional SRAM cell, different SRAM cell topologies (4T–11T) are discussed. The cells are designed using Tanner EDA tool with 180 nm technology. The variation of power and read delay of different cell topologies compared to conventional SRAM cell are considered. The behaviour of power against supply voltage Vdd for different cell topologies reveals that the higher cell topologies offer better stability by maintaining the power as low as possible.


SRAM cell Low power Read stability 


  1. 1.
    Takeda, K., et al.: A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications. IEEE J. Solid-State Circuits 41(1) (2006)CrossRefGoogle Scholar
  2. 2.
    Thakare, P.V., Tembhurne, S.: A power analysis of SRAM cell using 12T topology for faster data transmission. Int. J. Sci. Technol. Eng. 2, 441–446 (2016)Google Scholar
  3. 3.
    Singh, W., Kumar, A.G.: Design of 6T, 5T and 4T SRAM cell on various performance metrics. In: 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 899–904 (2015)Google Scholar
  4. 4.
    Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd ed. Prentice-Hall, Englewood Cliffs, NJ (2003)Google Scholar
  5. 5.
    Kiran, P.N.V., Saxena, N.: Design and analysis of different types SRAM cell topologies. In: IEEE Sponsored 2nd International Conference on Electronics and Communication System (ICECS 2015), pp. 167–173 (2015)Google Scholar
  6. 6.
    Kulkarni, J.P., Goel, A., Ndai, P., Roy, K.: A read-disturb-free, differential sensing 1R/1W Port, 8T bitcell array. IEEE Trans. Very Large Scale Integr. Syst. 19 (2011)CrossRefGoogle Scholar
  7. 7.
    Hamzaoglu, F., Zhang, K., Wang, Y., Ahn, H.J., Bhattacharya, U., Chen, Z., Ng, Y.G., Pavlov, A., Smits, K., Bohr, M.: A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology. IEEE J. Solid-State Circuits 44 (2009)CrossRefGoogle Scholar
  8. 8.
    Shamanna, G., Kshatri, B., Gaurav, R., Tew, Y.S., Marfatia, P., Raghavendra, Y., Naik, V.: Process technology and design parameter impact on SRAM Bit-cell sleep effectiveness. IEEE (2010)Google Scholar
  9. 9.
    Kumar, S.V., Noor, A.: Characterization and comparison of low power SRAM cells. J. Electron. Devices 11 (2011)Google Scholar
  10. 10.
    Majumdar, B., Basu, S.: Low power single bitline 6T SRAM cell with high read stability. In: International Conference on Recent Trends in Information Systems, pp. 169–174 (2011)Google Scholar

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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringModern Institute of Engineering & TechnologyHooghlyIndia
  2. 2.Department of Electronics & Communication EngineeringAsansol Engineering CollegeAsansolIndia
  3. 3.Department of PhysicsModern Institute of Engineering & TechnologyHooghlyIndia

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