Low-Power Subthreshold Adiabatic Logic for Combinational and Sequential Circuits

Abstract

The foremost idea dominating the ongoing trends in VLSI circuits is to offer large-scale integration coupled with extensive power reduction solutions. This significant increase in the gate switching energy has resulted in higher power decadence and a costly replacement of heat sinks. At such places to limit the dissolution of power, elective arrangements at various levels of contemplation are suggested. This power dissipation is significantly minimized by the adiabatic logic structure at the cost of circuit complexity to accomplish minimal power dissipation. A brief approach of the aforementioned is included in this paper introducing the adiabatic logic family SAL. The implementation of the 4-bit CLA and 2 × 1 multiplexer combinational circuit and the sequential circuit of D flip-flop using NAND gates validates the credibility of the logic. A graph has been plotted to show the effect of temperature on subthreshold adiabatic logic-based 4-bit CLA. It aims at comparing the effectiveness of adiabatic logic with respect to power dissipation and delay. The setup and hold time graphs for sequential circuits have been plotted, respectively. The simulation results obtained from the virtuoso environment of cadence tool suggest commendable threefold power reduction in the SAL topology as compared to the conventional adiabatic topology.