Abstract
A number of efforts have been recently devoted to fault modeling, fault simulation, and test generation for asynchronous circuits (Shi and Makris , 2004).
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M.C. Bhuvaneswari, S. Jayanthy, Cross-talk delay fault test generation, in Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems (Springer, 2015), ISBN 978-81-322-1958-3
S. Jayanthy, M.C. Bhuvaneswari, M. Prabhu, Simulation based ATPG for low power testing of crosstalk delay faults in asynchronous circuits. Int. J. Comput. Appl. Technol. 48(3), 241–252 (2013)
S. Jayanthy, M.C. Bhuvaneswari, Fuzzy Delay Model Based Fault Simulator for Crosstalk Delay Fault Test Generation in Asynchronous Sequential Circuits, vol. 40, Part 1 (Sadhana Indian Academy of Sciences, Feb 2015), pp. 107–119
F. Shi, Y. Makris, SPIN-SIM: logic and fault simulation for speed-independent circuits, in Proceedings of International Test Conference (2004)
F. Shi, Y. Makris, Testing delay faults in asynchronous handshake circuits, in Proceedings of ICCAD’06 (5–9 Nov 2006)
S. Sur-Kolay, M. Roncken, K. Stevens, P.P. Chaudhuri, R. Roy, Fsimac: a fault simulator for asynchronous sequential circuits, in Proceedings of the 9th Asian Test Symposium (2000), pp. 114–119
Acknowledgements
Tables 9.3, 9.4, 9.5, 9.6, and 9.7 and Analysis Sects. 9.4 and 9.5 of the results are reproduced by Jayanthy and Bhuvaneswari (2015) from Sadhana Academy Proceedings in Engineering Sciences. This is gratefully acknowledged.
Some parts of the chapters are reproduced from Jayanthy S. and Bhuvaneswari M.C. “Development of Algorithms for Test Generation and Simulation of Crosstalk Delay Faults in VLSI Circuits” Ph.D. Dissertation, ANNA University, Chennai, 2012. This is gratefully acknowledged.
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Jayanthy, S., Bhuvaneswari, M.C. (2019). Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits. In: Test Generation of Crosstalk Delay Faults in VLSI Circuits. Springer, Singapore. https://doi.org/10.1007/978-981-13-2493-2_9
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