Abstract
Test generation using deterministic algorithms is highly complex and time-consuming. To obtain a particular output value for a component, backtracing is required to determine its input values. It is difficult to handle components other than simple gates (Rudnick and Greenstein 1997). In a simulation-based approach, processing occurs in the forward direction only. Hence, complex component types are handled more easily. Test can be generated for any type of circuit and any type of fault can be simulated. In a simulation-based approach, a logic or fault simulator is used to select the best test to apply (Agrawal et al 1989).
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Jayanthy, S., Bhuvaneswari, M.C. (2019). ATPG for Crosstalk Delay Faults using Single-Objective Genetic Algorithm. In: Test Generation of Crosstalk Delay Faults in VLSI Circuits. Springer, Singapore. https://doi.org/10.1007/978-981-13-2493-2_5
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DOI: https://doi.org/10.1007/978-981-13-2493-2_5
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