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DearDRAM: Discard Weak Rows for Reducing DRAM’s Refresh Overhead

  • Xusheng Zhan
  • Yungang Bao
  • Ninghui Sun
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 908)

Abstract

Due to leakage current, DRAM devices need periodic refresh operations to maintain the validity of data in each DRAM cell. The shorter refresh period is, the more refresh overhead DRAM devices have to amortize. Since the retention time of DRAM cells are different because of process variation, DRAM providers usually set default refresh period as the retention time of those weakest cells that account for less than 0.1% of total capacity.

In this paper, we propose DearDRAM (Discard weak rows DRAM), an efficient refresh approach that is able to substantially reduce refresh overhead using two mechanisms: selectively disabling weak rows and remapping their physical addresses to a reserved region. DearDRAM allows DRAM devices to perform refresh operations with a much longer period (increasing from 64 ms to 256 ms), which reduces energy consumption. It is worth noting that compared to previous schemes, DearDRAM is easy to be implemented, does not modify DRAM chip and only introduces slight modifications to memory controller. Experimental results show that DearDRAM can save refresh energy an average of 76.12%, save total energy about 12.51% and improve IPC an average of 4.56% in normal temperature mode.

Keywords

DRAM Memory controller Refresh Weak cell 

References

  1. 1.
    Barroso, L.A., Clidaras, J., Holzle, U.: The datacenter as a computer: an introduction to the design of warehouse-scale machines. Synth. Lect. Comput. Archit. 8(3), 1–154 (2013)CrossRefGoogle Scholar
  2. 2.
    Jacob, B., Ng, S., Wang, D.: Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann (2010)Google Scholar
  3. 3.
    Kim, K., Lee, J.: A new investigation of data retention time in truly nanoscaled DRAMs. IEEE Electron Device Lett. 30(8), 846–848 (2009)CrossRefGoogle Scholar
  4. 4.
    Li, Y., Schneider, H., Schnabel, F.: DRAM yield analysis and optimization by a statistical design approach. IEEE Trans. Circuits Syst. I Regul. Pap. 58(12), 2906–2918 (2011)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Liu, J., Jaiyen, B., Veras, R.: RAIDR: retention-aware intelligent DRAM refresh. ACM SIGARCH Comput. Architect. News 40(3), 1–12 (2012)CrossRefGoogle Scholar
  6. 6.
    Wang, J., Dong, X., Xie, Y.: ProactiveDRAM: a DRAM-initiated retention management scheme. In: 2014 32nd IEEE International Conference on Computer Design (ICCD), pp. 22–27. IEEE (2014)Google Scholar
  7. 7.
    Mukundan, J., Hunter, H., Kim, K.: Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ACM SIGARCH Comput. Architect. News 41(3), 48–59 (2013)CrossRefGoogle Scholar
  8. 8.
    Bhati, I., Chishti, Z., Lu, S.L.: Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. ACM SIGARCH Comput. Architect. News 43(3), 235–246 (2015)CrossRefGoogle Scholar
  9. 9.
    JEDEC, DDR4 sdram specification (2012)Google Scholar
  10. 10.
    Binkert, N., Beckmann, B., Black, G.: The gem5 simulator. ACM SIGARCH Comput. Architect. News 39(2), 1–7 (2011)CrossRefGoogle Scholar
  11. 11.
    Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Architect. News 34(4), 1–17 (2006)CrossRefGoogle Scholar
  12. 12.
    Kim, Y., Seshadri, V., Lee, D.: A case for exploiting subarray-level parallelism (SALP) in DRAM. ACM SIGARCH Comput. Architect. News 40(3), 368–379 (2012)CrossRefGoogle Scholar
  13. 13.
    Snavely, A., Tullsen, D.M.: Symbiotic jobscheduling for a simultaneous mutlithreading processor. ACM SIGPLAN Not. 35(11), 234–244 (2000)CrossRefGoogle Scholar
  14. 14.
    Stuecheli, J., Kaseridis, D., Hunter, H.C., et al.: Elastic refresh: techniques to mitigate refresh penalties in high density memory. In: 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 375–384 (2010)Google Scholar
  15. 15.
    Venkatesan, R.K., Herr, S., Rotenberg, E.: Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. The Twelfth International Symposium on High-Performance Computer Architecture, pp. 155–165. IEEE (2006)Google Scholar
  16. 16.
    Liu, J., Jaiyen, B., Kim, Y.: An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms. ACM SIGARCH Comput. Architect. News 41(3), 60–71 (2013)CrossRefGoogle Scholar
  17. 17.
    Khan, S., Lee, D., Kim, Y.: The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study. ACM SIGMETRICS Perform. Eval. Rev. 42(1), 519–532 (2014)CrossRefGoogle Scholar
  18. 18.
    Rosenfeld, P., Cooper-Balis, E., Jacob, B.: DRAMSim2: a cycle accurate memory system simulator. IEEE Comput. Architect. Lett. 10(1), 16–19 (2011)CrossRefGoogle Scholar
  19. 19.
    Rixner, S., Dally, W.J., Kapasi, U.J.: Memory access scheduling. ACM SIGARCH Comput. Architect. News 28(2), 128–138 (2000)CrossRefGoogle Scholar
  20. 20.
    Kotra, J.B., Shahidi, N., Chishti, Z.A., et al.: Hardware-software co-design to mitigate dram refresh overheads: a case for refresh-aware process scheduling. In: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 723–736. ACM (2017)Google Scholar
  21. 21.
    Malladi, K.T., Lee, B.C., Nothaft, F.A.: Towards energy-proportional datacenter memory with mobile DRAM. ACM SIGARCH Comput. Architect. News 40(3), 37–48 (2012)CrossRefGoogle Scholar
  22. 22.
    Cui, Z., McKee, S.A., Zha, Z., et al. DTail: a flexible approach to DRAM refresh management. In: Proceedings of the 28th ACM International Conference on Supercomputing, pp. 43–52. ACM (2014)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.State Key Laboratory of Computer ArchitectureICT, CASBeijingChina
  2. 2.University of Chinese Academy of SciencesBeijingChina

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