Abstract
Because of the human brain’s parallel computing structure and its characteristics of the localized storage, the human brain has great superiority of high throughput and low power consumption. Based on the bionics of the brain, many researchers try to imitate the behavior of neurons with hardware platform so that we can obtain the same or close computational acceleration performance like the brain. In this paper, we proposed a hardware structure to implement single neuron with Integration-and-Fire(IF) model on Virtex-7 XC7VX485T-ffg1157 FPGA. Through simulation and synthesis, we quantitatively analyzed the device utilization and power consumption of our structure; meanwhile, the function of the proposed hardware implementation is verified with the classic XOR benchmark with a 4-layer SNN and the scalability of our hardware neuron is tested with a handwritten digits recognition mission on MNIST database using a 6-layer SNN. Experimental results show that the neuron hardware implementation proposed in this paper can pass the XOR benchmark test and fulfill the need of handwritten digits recognition mission. The total on-chip power of 4-layer SNN is 0.114 W, which is the lowest among the ANN and firing-rate based SNN at the same scale.
Supported by Advanced General Chip, Project Name: The Design of Supercomputer Chip, NO. 2017ZX01028-103.
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Wang, S. et al. (2018). A Power Efficient Hardware Implementation of the IF Neuron Model. In: Li, C., Wu, J. (eds) Advanced Computer Architecture. ACA 2018. Communications in Computer and Information Science, vol 908. Springer, Singapore. https://doi.org/10.1007/978-981-13-2423-9_11
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DOI: https://doi.org/10.1007/978-981-13-2423-9_11
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