Abstract
Cache replacement policies play important roles in efficiently processing the current big data applications. The performance of any high performance computing system is highly depending on the performance of its cache memory. A better replacement policy allows the important blocks to be placed nearer to the core. Hence reduces the overall execution latency and gives better computational efficiency. There are different replacement policies exits. The main difference among these policies is how to select the victim block from the cache such that it can be replaced with another newly fetched block. Non-optimal replacement policy may remove important blocks from the cache when some less important (dead) blocks also present in the cache. Proposing better replacement policy for cache memory is a major research area from last three decades. The most widely used replacement policies used for classical cache memories are Least Recently Used Policy (LRU), Random Replacement Policy or Pseudo-LRU. As the technology advances the technology of cache memory is also changing. For efficient processing of big data based applications today’s computer having high performance computing ability requires larger cache memory. Such larger cache memory makes the task of replacement policies more challenging. In this paper we have done a survey about the innovations done in cache replacement policies to support the efficient processing of big data based applications.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Balasubramonian, R., Jouppi, N.P., Muralimanohar, N.: Multi-Core Cache Hirarchies. Morgan and Claypool, California (2011)
Chen, Z., Xiao, N., Lu, Y., Liu, F.: Me-CLOCK: a memory-efficient framework to implement replacement policies for large caches. IEEE Trans. Comput. 65(8), 2665–2671 (2016)
Kharbutli, M., Sheikh, R.: LACS: a locality-aware cost-sensitive cache replacement algorithm. IEEE Trans. Comput. 63(8), 1975–1987 (2014)
Kim, C., Burger, D., Keckler, S.W.: An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. SIGOPS Oper. Syst. Rev. 36, 211–222 (2002)
Chishti, Z., Powell, M.D., Vijaykumar, T.N.: Distance associativity for high-performance energy-efficient non-uniform cache architectures. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 55–66 (2003)
Liu, H., Ferdman, M.,. Huh, J, Burger, D.: Cache bursts: a new approach for eliminating dead blocks and increasing cache efficiency. In: 2008 41st IEEE/ACM International Symposium on Microarchitecture, pp. 222–233, November 2008
Khan, S.M., Jim´enez, D.A., Burger, D., Falsafi, B.: Using dead blocks as a virtual victim cache. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques. PACT 2010, pp. 489–500 (2010)
Das, S., Kapoor, H.K.: Latency aware block replacement for L1 caches in chip multiprocessor. In: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 182–187, July 2017
Kharbutli, M., Solihin, Y.: Counter-based cache replacement and bypassing algorithms. IEEE Trans. Comput. 57(4), 433–447 (2008)
Wang,Y., Zhang, L., Han, Y., Li, H., Li, X.: Address remapping for static NUCA in NoC-based degradable chip-multiprocessors. In: Proceedings of the IEEE 16th Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 70–76, December 2010
Huh, J., Kim, C., Shafi, H., Zhang, L., Burger, D., Keckler, S.W.: A NUCA substrate for flexible CMP cache sharing. In: Proceedings of the 19th Annual International Conference on Supercomputing. ICS 2005, pp. 31–40 (2005)
Belady, L.A.: A study of replacement algorithms for a virtual-storage computer. IBM Syst. J. 5(2), 78–101 (1966)
Das, S., Polavarapu, N., Halwe, P.D., Kapoor, H.K.: Random-LRU: a replacement policy for chip multiprocessors. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds.) VDAT 2013. CCIS, vol. 382, pp. 204–213. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-42024-5_25
Jeong, J., Dubois, M.: Optimal replacements in caches with two miss costs. In: Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures. SPAA 1999, pp. 155–164 (1999)
Jeong, J., Dubois, M.: Cost-sensitive cache replacement algorithms. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture. HPCA 2003, pp. 327–337 (2003)
Wong, W.A., Baer, J.L.: Modified LRU policies for improving second-level cache behavior. In: Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No. PR00550), pp. 49–60 (2000)
Jaleel, A., Theobald, K.B., Steely, Jr., S.C., Emer, J.: High performance cache replacement using re-reference interval prediction (RRIP). In: Proceedings of the 37th Annual International Symposium on Computer Architecture. ISCA 2010, pp. 60–71 (2010)
Ju, R.D.-C., Lebeck, A.R., Wilkerson, C.: Locality vs. criticality. In: Srinivasan, S.T. (ed.) Proceedings of the 28th Annual International Symposium on Computer Architecture. ISCA 2001, pp. 132–143 (2001)
Keramidas, G., Petoumenos, P., Kaxiras, S.: Cache replacement based on reuse-distance prediction. In: 2007 25th International Conference on Computer Design, pp. 245–250, October 2007
Rajan, K., Ramaswamy, G.: Emulating optimal replacement with a shepherd cache. In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), pp. 445–454, December 2007
Zebchuk,J., Makineni, S., Newell, D.: Re-examining cache replacement policies. In: 2008 IEEE International Conference on Computer Design, pp. 671–678, October 2008
Lee, D., et al.: LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies. IEEE Trans. Comput. 50(12), 1352–1361 (2001)
Qureshi, M.K., Jaleel, A., Patt, Y.N., Steely, S.C., Emer, J.: Adaptive insertion policies for high performance caching. In: Proceedings of the 34th Annual International Symposium on Computer Architecture. ISCA 2007, pp. 381–391 (2007)
Jaleel, A., Hasenplaugh, W., Qureshi, M., Sebot, J., Steely, Jr., S., Emer, J.: Adaptive insertion policies for managing shared caches. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, pp. 208–219 (2008)
Chaudhuri,M.: Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. In: 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 401–412, December 2009
Qureshi, M.K., Lynch, D.N., Mutlu, O., Patt, Y.N.: A case for MLP-aware cache replacement. SIGARCH Comput. Archit. News 34(2), 167–178 (2006)
Mittal, S., Vetter, J.S., Li, D.: A survey of architectural approaches for managing embedded dram and non-volatile on-chip caches. IEEE Trans. Parallel Distrib. Syst. 26(6), 1524–1537 (2015)
He, J., Callenes-Sloan, J.: A novel architecture of large hybrid cache with reduced energy. IEEE Trans. Circuits Syst. I Regul. Pap. 64(12), 3092–3102 (2017)
Sheikh, R., Kharbutli, M.: Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms. In: 2010 IEEE International Conference on Computer Design (ICCD), pp. 76–83, October 2010
Suh, G.E., Rudolph, L., Devadas, S.: Dynamic partitioning of shared cache memory. J. Supercomput. 28(1), 7–26 (2004)
Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches. In: 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2006), pp. 423–432, December 2006
Sundararajan, K., Porpodas, V., Jones, T., Topham, N., Franke, B.: Cooperative partitioning: energy-efficient cache partitioning for high-performance CMPs. In: 2012 IEEE 18th International Symposium on High Performance Computer Architecture (HPCA), pp. 1–12 (2012)
Xie, Y., Loh, G.H.: PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. SIGARCH Comput. Archit. News 37(3), 174–183 (2009)
Halwe, P.D., Das, S., Kapoor, H.K.: Towards a better cache utilization using controlled cache partitioning. In: 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, pp. 179–186, December 2013
Qureshi, M.K., Thompson, D., Patt, Y.N.: The V-Way cache: demand based associativity via global replacement. ACM SIGARCH Comput. Architect. News 33(2), 544–555 (2005)
Sanchez, D., Kozyrakis, C.: The ZCache: decoupling ways and associativity. In: Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 187–198 (2010)
Das, S., Kapoor, H.K.: Exploration of migration and replacement policies for dynamic NUCA over tiled CMPs. In: Proceedings of the 28th International Conference on VLSI Design (VLSID) (2015)
Das, S., Kapoor, H.K.: Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsyst. 38(4), 263–275 (2014)
Das, S., Kapoor, H.K.: Dynamic associativity management using fellow sets. In: Proceedings of the 2013 International Symposium on Electronic System Design (ISED), pp. 133–137 (2013)
Binkert, N., et al.: The Gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)
Martin, M.M.K., et al.: Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News 33(4), 92–99 (2005). http://www.cs.wisc.edu/gems/
Agarwal, N., Krishna, T., Peh, L.-S., Jha, N.: GARNET: a detailed on-chip network model inside a full-system simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS 2009, pp. 33–42, April 2009
Muralimanohar, N., Balasubramonian, R., Jouppi, N.: Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 40, pp. 3–14 (2007)
Magnusson, P.S., et al.: Simics: a full system simulation platform. Computer 35(2), 50–58 (2002). \http://www.simics.net
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Das, P. (2019). Role of Cache Replacement Policies in High Performance Computing Systems: A Survey. In: Verma, S., Tomar, R., Chaurasia, B., Singh, V., Abawajy, J. (eds) Communication, Networks and Computing. CNC 2018. Communications in Computer and Information Science, vol 839. Springer, Singapore. https://doi.org/10.1007/978-981-13-2372-0_35
Download citation
DOI: https://doi.org/10.1007/978-981-13-2372-0_35
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-2371-3
Online ISBN: 978-981-13-2372-0
eBook Packages: Computer ScienceComputer Science (R0)