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Properties and Performance of Linearly Extensible Multiprocessor Interconnection Networks

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Abstract

Interconnection networks arise as the basic bone of research related to parallel computing, high-performance system design, distributed computing or computer networks. There has been a strong interest in the design of modern interconnection topologies to achieve the desired performance. This paper presents the performance study of a new class of parallel architectures known as linearly extensible multiprocessor architectures. It describes the properties and parameters to evaluate the performance of newly designed interconnection networks. The comparative study is carried out which shows that the proposed class posses the desirable topological properties of hypercube as well as tree type topologies. The performance of these architectures is also evaluated in terms of load balancing by applying standard scheduling algorithm on them. The simulation results show that the proposed architectures are performing on equal footing and their performance are compatible with standard hypercube architecture. The comparative study implies the various aspects while designing and efficient multiprocessor interconnection network.

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References

  1. Koibuchi, M., Fujiwara, I., Matsutani, H., Casanova, H.: Layout-conscious random topologies for HPC off-chip interconnect. In: 19th International Conference on High-Performance Computer Architecture (HPCA), pp. 484–495 (2013)

    Google Scholar 

  2. Le, N.T., Nguyen, V.K.: Interconnection networks with efficient custom routing, exploiting small-world effect. In: IEEE International Conference on Computing and Communication Technologies-Research, Innovation, and Vision for the Future (RIVF), pp. 41–46 (2013)

    Google Scholar 

  3. Prasad, N., Mukkherjee, P., Chattopadhyay, S., Chakrabarti, I.: Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distrib. Comput. 113, 17–36 (2018)

    Article  Google Scholar 

  4. Monemizadeh, M., Azad, H.S.: The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors. In: ACM Symposium on Applied Computing, pp. 729–733 (2005)

    Google Scholar 

  5. Mohanty, S.P., Ray, B.N., Patro, N.S., Tripathy, A.R.: Topological properties of a new fault tolerant interconnection network for parallel computer. In: Proceeding of ICIT International Conference on Information Technology, pp. 36–40 (2008)

    Google Scholar 

  6. Khan, Z.A., Siddiqui, J., Samad, A.: Topological evaluation of variants hypercube network. Asian J. Comput. Sci. Inf. Technol. 3(9), 125–128 (2013)

    Google Scholar 

  7. Alam, M., Varshney, A.K.: A comparative study of interconnection network. Int. J. Comput. Appl. (0975-8887) 127(4), 37–43 (2015)

    Google Scholar 

  8. Patelm, A., Kasalik, A., McCrosky, C.: Area efficient VLSI layout for binary hypercube. IEEE Trans. Comput. 49(2), 160–169 (2006)

    Article  MathSciNet  Google Scholar 

  9. Khan, Z.A., Siddiqui, J., Samad, A.: Performance analysis of massively parallel architectures. BVICAM’s Int. J. Inf. Technol. 5(1), 563–568 (2013)

    Google Scholar 

  10. Samad, A., Rafiq, M.Q., Farooq, O.: LEC: an efficient scalable parallel interconnection network. In: Proceeding of International Conference on Emerging Trends in Computer Science, Communication and Information Technology, Nanded, India, pp. 453–458 (2010)

    Google Scholar 

  11. Khan, Z.A., Siddiqui, J., Samad, A.: Linear crossed cube (LCQ): a new interconnection network topology for massively parallel architectures. Int. J. Comput. Netw. Inf. Sci. (IJCNIS) 7(3), 18–25 (2015). ISSN/ISBN NO: 2074-9090

    Google Scholar 

  12. Manullah: A Δ-based linearly extensible multiprocessor network. Int. J. Comput. Sci. Inf. Technol. 4(5), 700–707 (2013)

    Google Scholar 

  13. Ding, Z., Hoare, R.R., Jones, K.A.: Level-wise scheduling algorithm for fat tree interconnection networks. In: Proceedings of the 2006 ACM/IEEE SC|06 Conference (SC 2006), pp. 9–17 (2006)

    Google Scholar 

  14. Mahafzah, B.A., Jaradat, B.A.: The hybrid dynamic parallel scheduling algorithm for load balancing on chained-cubic tree. J. Supercomput. 52, 224–252 (2010)

    Article  Google Scholar 

  15. Dutot, P.: Complexity of master-slave tasking on heterogeneous trees. Eur. J. Oper. Res. 164(3), 690–695 (2005)

    Article  MathSciNet  Google Scholar 

  16. Haung, K., Wang, Z., Weng, X., Lin, W.: A scheduling algorithm on heterogeneous star and tree grid computing platform. In: International Conference on Convergence Information Technology, pp. 347–351. IEEE (2007). https://doi.org/10.1109/icct.2007.275

  17. Birmpilis, S., Aslanidis, T.: A critical improvement on open shop scheduling algorithm for routing in interconnection networks. Int. J. Comput. Netw. Commun. (IJCNC) 9(1), 1–19 (2017)

    Google Scholar 

  18. Samad, A., Khan, Z.A., Siddiqui, J.: Optimal dynamic scheduling algorithm for cube based multiprocessor interconnection networks. Int. J. Control Theory Appl. 9(40), 485–490 (2016)

    Google Scholar 

  19. Mohammad, S.B., Ababneh, I.: I Improving system performance in non-contiguous processor allocation for mesh interconnection networks. Int. J. Simul. Model. Pract. Theory 80, 19–31 (2018)

    Article  Google Scholar 

  20. Samad, A., Rafiq, M.Q., Farooq, O.: Two round scheduling (TRS) scheme for linearly extensible multiprocessor systems. Int. J. Comput. Appl. 38(10), 34–40 (2012)

    Google Scholar 

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Gautam, S., Samad, A. (2019). Properties and Performance of Linearly Extensible Multiprocessor Interconnection Networks. In: Verma, S., Tomar, R., Chaurasia, B., Singh, V., Abawajy, J. (eds) Communication, Networks and Computing. CNC 2018. Communications in Computer and Information Science, vol 839. Springer, Singapore. https://doi.org/10.1007/978-981-13-2372-0_1

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  • DOI: https://doi.org/10.1007/978-981-13-2372-0_1

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-2371-3

  • Online ISBN: 978-981-13-2372-0

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