Abstract
Coarse-grained Reconfigurable Array (CGRA) is suitable candidate hardware architecture for many computation-intensive applications due to its flexibility and efficiency. In current CGRA architecture, each Processing Element (PE) in CGRA performs one operation or transfers data onto neighbors per cycle. In this paper, a dual-issue scheme is proposed to execute Data Acyclic Graph (DAG). Two operations with mutual precedents can be executed at the same cycle in the PE in the proposed design to improve efficiency. Since some hardware is shared by operations, the overhead can be lowered. We also proposed an ant colony based algorithm for mapping DAG to dual-issue CGRA. Experimental results demonstrate that dual-issue CGRA consumes 5.24% less hardware resource while the performance of some DAG improved 2.6%.
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Zainul, A., Svensson, B.: Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocess. Microsyst. 33(3), 161–178 (2009)
Sangyun, O., Hongsik, L., Jongeun, L.: Efficient execution of stream graphs on coarse-grained reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12), 1978–1988 (2017)
Xitian, F., Di, W., Wei, C., Wayne, L., Lingli, W.: Stream processing dual-track CGRA for object inference. IEEE Trans. Very Larg. Scale Integr. (VLSI) Syst. 26, 1–14 (2018)
Chattopadhyay, A.: Ingredients of adaptability: a survey of reconfigurable processors. VLSI Design 2013, 1–18 (2013)
Hamzeh, M., Shrivastava, A., Sarma, B.K.: Branch-aware loop mapping on CGRAs. In: Proceedings of 2014 Design Automation Conference (DAC), pp. 1–6. IEEE, San Francisco (2014)
Tajas, R., Lukas, J., Dennis, W., Christian, H.: Scheduler for inhomogeneous and irregular CGRAs with support for complex control flow. In: Proceedings of 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 198–207 (2016)
Radhika, S.H.R., Shrivastava, A., Hamzeh, M.: Path selection based acceleration of conditionals in CGRAs. In: Proceedings of 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 121–126. IEEE, Grenoble (2015)
Zhou, L., Liu, D., Zhang, B., Liu, H.: Ant colony optimization for application mapping in coarse-grained reconfigurable array. In: Brisk, P., de Figueiredo Coutinho, J.G., Diniz, P.C. (eds.) ARC 2013. LNCS, vol. 7806, p. 219. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-36812-7_22
Merkle, D., Middendorf, M.: Fast ant colony optimization on runtime reconfigurable processor arrays. Genet. Progr. Evol. Mach. 3(4), 345–361 (2002)
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This paper is supported by the National Natural Science Foundation of China (61602496).
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Zhou, L., Zhang, J., Liu, H. (2018). Dual-Issue CGRA for DAG Acceleration. In: Zhou, Q., Gan, Y., Jing, W., Song, X., Wang, Y., Lu, Z. (eds) Data Science. ICPCSEE 2018. Communications in Computer and Information Science, vol 901. Springer, Singapore. https://doi.org/10.1007/978-981-13-2203-7_40
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DOI: https://doi.org/10.1007/978-981-13-2203-7_40
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