Exploring Low Power Design Through Performance Analysis of FinFET for Fin Shape Variations

  • Sangeeta MangeshEmail author
  • P. K. Chopra
  • K. K. Saini
  • Amit Saini
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 757)


With concern of global warming, low power design is an important research domain for scientist and engineers. Focusing upon the energy saving trend, this paper compares the performance analysis of all possible fin shapes in a 16 nm Bulk FinFET device from low power design perspective. Performance metrics include transconductance, transconductance generation factor (TGF), on/off current ratio, Subthreshold swing (SS), Drain Induced Barrier Lowering (DIBL) and power consumption. Low power system design feasibility with the optimized round fin shape resulting from the comparative analysis is justified by implementing N and P FinFET devices with perfectly matched VI characteristics. Prospective usage to meet recent developments in system design and control engineering with power optimization and scalability success in round FinFET device is also reviewed through this work.


SS-Subthreshold swing DIBL-Drain induced barrier lowering FOM-Figure of merit 


  1. 1.
    Moore, M.: International Technology Roadmap (2015)Google Scholar
  2. 2.
    Ferain, I., Colinge, C.A., Colinge, J.-P.: Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011)CrossRefGoogle Scholar
  3. 3.
    Yi-Bo, Z., Lei, S., Hao, X., Jing-Wen, H., Yi, W., Sheng-Dong, Z.: Comparative study of silicon nanowire transistors with triangular-shaped cross sections. Jpn. J. Appl. Phys. 54, 04DN01 (2015)CrossRefGoogle Scholar
  4. 4.
    Fasarakis, N., Tassis, D.H., Tsormpatzoglou, A., Papathanasiou, K., Dimitriadis, C.A.: Compact modeling of Nano-Scale Trapezoidal Cross-Sectional FinFETs, pp. 13–16. IEEE, Piscataway (2013)Google Scholar
  5. 5.
    Gaynor, B.D., Hassoun, S.: Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design. IEEE Trans. Electron Devices 61, 2738–2744 (2014)CrossRefGoogle Scholar
  6. 6.
    Nam, H., Shin, C.: Impact of current flow shape in tapered (versus rectangular) FinFET on threshold voltage variation induced by work-function variation. IEEE Trans. Electron Devices 61, 2007–2011 (2014)CrossRefGoogle Scholar
  7. 7.
    Xu, W., Yin, H., Ma, X., Hong, P., Xu, M., Meng, L.: Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate. Nanoscale Res. Lett. 10, 249 (2015)CrossRefGoogle Scholar
  8. 8.
    Li, Y., Hwang, C.H.: Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs. IEEE Trans. Electron Devices 54, 3426–3429 (2007)CrossRefGoogle Scholar
  9. 9.
    Shukla, S., Gill, S.S., Kaur, N., Jatana, H.S., Nehru, V.: Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET. Active and Passive Electronic Components (2017)Google Scholar
  10. 10.
    Yeap, G.K.: Practical Low Power Digital VLSI Design (1998)CrossRefGoogle Scholar
  11. 11.
    Cao, Y.: Predictive Technology Model for Robust Nanoelectronic Design (2011)Google Scholar
  12. 12.
    Boukortt, N., Hadri, B., Patanè, S., Caddemi, A., Crupi, G.: Electrical Characteristics of 8-nm SOI n-FinFETs. Silicon 8, 497–503 (2016)CrossRefGoogle Scholar
  13. 13.
    Bhattacharya, D., Jha, N.K.: FinFETs: From Devices to Architectures. Adv. Electron. 2014, 1–21 (2014)CrossRefGoogle Scholar
  14. 14.
    Mangesh, S., Chopra, P.K., Saini, K.K.: Quantum effect in Nanoscale SOI FINFET device structure: a simulation study. In: Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit, DevIC 2017 (2017)Google Scholar
  15. 15.
    Vidya, V., Sciences, C.: Thin-Body Silicon FET Devices and Technology. Spring (2007)Google Scholar
  16. 16.
    Chauhan, Y.S., Lu, D.D., Venugopalan, S., Karim, M.A., Niknejad, A., Hu, C.: Compact Models for sub-22 nm MOSFETs 2, pp. 720–725 (2011)Google Scholar
  17. 17.
    Genius Simulator User’s Guide from CogendaGoogle Scholar
  18. 18.
    Mohapatra, S.K., Pradhan, K.P., Sahu, P.K., Kumar, M.R.: The performance measure of GS-DG MOSFET: An impact of metal gate work function. Adv. Nat. Sci. Nanosci. Nanotechnol. 5 (2014)Google Scholar
  19. 19.
    Eng, Y.C., Hu, L., Chang, T.F., Hsu, S., Chiou, C.M., Wang, T., Yang, C.W., Lin, C.T., Wang, I.C., Chen, M.C., Lai, A., Wang, P.W., Hsu, C.J., Pang, W.Y., Kuo, C.H., Cheng, O., Wang, C.Y.: A new figure of merit, Δ VDIBLSS/(Id, sat/Isdleak), to characterize short-channel performance of a bulk-Si n-channel FinFET device. IEEE J. Electron Devices Soc. 5, 18–22 (2017)CrossRefGoogle Scholar
  20. 20.
    Yeh, W.K., Zhang, W., Yang, Y.L., Dai, A.N., Wu, K., Chou, T.H., Lin, C.L., Gan, K.J., Shih, C.H., Chen, P.Y.: The observation of width quantization impact on device performance and reliability for High-k/metal tri-gate FinFET. IEEE Trans. Device Mater. Reliab. 16, 610–616 (2016)CrossRefGoogle Scholar
  21. 21.
    Rabaey, J.M., Pedram, M.: Low Power Design Methodology (1996)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Sangeeta Mangesh
    • 1
    Email author
  • P. K. Chopra
    • 2
  • K. K. Saini
    • 3
  • Amit Saini
    • 4
  1. 1.A.P.J. Abdul Kalam Technical UniversityLucknowIndia
  2. 2.Department of Electronics & Communication EngineeringAjay Kumar Garg Engineering CollegeGhaziabadIndia
  3. 3.National Physical LaboratoriesNew DelhiIndia
  4. 4.Cadre Design SystemsDelhiIndia

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