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Exploring Low Power Design Through Performance Analysis of FinFET for Fin Shape Variations

  • Sangeeta MangeshEmail author
  • P. K. Chopra
  • K. K. Saini
  • Amit Saini
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 757)

Abstract

With concern of global warming, low power design is an important research domain for scientist and engineers. Focusing upon the energy saving trend, this paper compares the performance analysis of all possible fin shapes in a 16 nm Bulk FinFET device from low power design perspective. Performance metrics include transconductance, transconductance generation factor (TGF), on/off current ratio, Subthreshold swing (SS), Drain Induced Barrier Lowering (DIBL) and power consumption. Low power system design feasibility with the optimized round fin shape resulting from the comparative analysis is justified by implementing N and P FinFET devices with perfectly matched VI characteristics. Prospective usage to meet recent developments in system design and control engineering with power optimization and scalability success in round FinFET device is also reviewed through this work.

Keywords

SS-Subthreshold swing DIBL-Drain induced barrier lowering FOM-Figure of merit 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Sangeeta Mangesh
    • 1
    Email author
  • P. K. Chopra
    • 2
  • K. K. Saini
    • 3
  • Amit Saini
    • 4
  1. 1.A.P.J. Abdul Kalam Technical UniversityLucknowIndia
  2. 2.Department of Electronics & Communication EngineeringAjay Kumar Garg Engineering CollegeGhaziabadIndia
  3. 3.National Physical LaboratoriesNew DelhiIndia
  4. 4.Cadre Design SystemsDelhiIndia

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