Abstract
Multipliers are used in arithmetic and logic unit (ALU) and the performance of multiplier greatly depends on the number of adder cells. A study and performance investigation of array multiplier using low-power 10T full adder is presented. One of the crucial circuits in all digital devices is the adder cell and it is used in ALU. In this work, various performance parameters including power consumption, delay, and power-delay product are compared with full adder, array multiplier using 10T full-adder and static energy-recovery full (SERF) adder-based techniques. Array multipliers realized that using 10T-based full-adder circuit consumes less power when compared to SERF techniques. Simulation results show that the power consumption of array multiplier using 10T full-adder and SERF technique is 673.7 µW and 1.042 mW, respectively, which is less than the power consumption of conventional array multiplier. The power consumption and delay of proposed Array Multiplier are obtained using 180nm CMOS process.
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References
Ravi1, N., Satish, A., Dr. Jayachandra Prasad, T., Dr. Subba Rao, T.: A new design for array multiplier with trade off in power and area. IJCSI, 8, 1–5 (2011)
Vamsi Krishnai, B., Dhaunjaya, K.: Analysis and modeling of low power array multipliers using cadence virtuoso simulator in 45 nm technology. IJECIERD. 3(4) (2013)
Jhamb, M., Garima, Lohani, H.: Design implementation and performance comparison of multiplier topologies in power-delay space. Jestech. 355–363 (2015)
Shams, A.M., Darwish, T.K., Bayoumi, M.A.: Performance analysis of low-power 1-Bit CMOS full adder cells. IEEE Trans. On VLSI Syst. 10, 20–29 (2002)
Mathew, K., Asha Latha, S., Ravi, T., Logashanmugam, E.: Design and analysis of an array multiplier using an area efficient full adder cell in 32 nm CMOS technology. IJES. 2, 8–16 (2013)
Navi, K., Maeen, M., Hashemipou, O.: An energy efficient full adder cell for low voltage. IEICE. 2(2), 553–559
Manjunath, K.M.: Analysis of various full-adder circuits in cadence, 30–38 (2015)
Navi, K., Kavehei Shahid, O.: Low-power and high-performance 1-Bit CMOS full-adder cell. J. Comput. 3(2) (2008)
Yadav, M., Gupta, A., Rai, S.: A study and comparative analysis of low power hybrid-CMOS 1-bit full adders in deep-submicron technology. In; IEEE International Conference in Power,Control and Embedded Systems, pp. 1–7, ICPCES (2017)
Bui, H.T., Wang, Y., Jiang, Y.: Design and analysis of low-power 10-transistor full adders using novel XOR XNOR gates. IEEE Trans. Circuits Syst.-II: Analog Digital Signal Proc. 49, 25–30 (2002)
Kumar Pankaj and: R. K. Sharma: Low voltage high performance hybrid full adder, Engineering Science and Technology an. International Journal 19(1), 559–565 (2016)
Hernandez, M.A., Linares-Aranda, M.: CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(4) (2011)
Chang, C.-H., Gu, J., Zhang, M.:A review of 0.18 μm full Adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13(6), 686–695 (2005)
Goel, S., Kumar, A., Bayoumi, M.A.: Design of robust energy-efficient Full Adders for deep-sub micrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(12), 1309–1321 (2006)
Zhang. M., Gu, J., Chang, C. H.: A novel hybrid pass logic with static CMOS output drive full-adder cell. Proc. IEEE Int. Symp. Circuits Syst. 317–320(2003)
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The authors are grateful to the management of Karunya Institute of Technology and Sciences (KITS) for providing necessary facilities in VLSI laboratory to carry out this work.
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Shylu Sam, D.S., Roseline, A.C. (2019). Performance Analysis of Array Multiplier Using Low-Power 10T Full Adder. In: Satapathy, S., Bhateja, V., Das, S. (eds) Smart Intelligent Computing and Applications . Smart Innovation, Systems and Technologies, vol 104. Springer, Singapore. https://doi.org/10.1007/978-981-13-1921-1_28
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DOI: https://doi.org/10.1007/978-981-13-1921-1_28
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