Abstract
Prototype developments of cognitive radio sensor nodes (CRSNs) need to minimize the utilization of hardware and power consumption as they have an inherent limitation in terms of transmission power consumption, communication capabilities, processing speed, and memory resources. In this paper, a power-sharing algorithm based on game theory is implemented in FPGA for an embedded wireless system in which both Primary User (PU) and CRSN operate simultaneously and a dedicated hardware unit takes the decision about the power transmission for both PU and CRSN. Hardware architecture is designed in Verilog hardware description language in Vivado Design Suite 2015.3 using IEEE 754 floating point format with 64-bit double-precision. The hardware module analyzed in real time in DIGILENT ZED BOARD (xcz-7z020 clg484-1) using integrated logic analyzer shows computational time and computational power of 4.55 µs and 9 mw, respectively. Comparative performance analysis of the hardware and MATLAB simulation shows that the former provides less computing power to CRSN compared to the simulated value. However, number of iteration varies in simulation for the distance of the node from the base station whereas it is almost constant in the hardware module.
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Roy Chatterjee, S., Chowdhury, J., Chakraborty, M. (2019). Hardware Realization of Power Adaptation Technique for Cognitive Radio Sensor Node. In: Chakraborty, M., Chakrabarti, S., Balas, V., Mandal, J. (eds) Proceedings of International Ethical Hacking Conference 2018. Advances in Intelligent Systems and Computing, vol 811. Springer, Singapore. https://doi.org/10.1007/978-981-13-1544-2_16
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DOI: https://doi.org/10.1007/978-981-13-1544-2_16
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