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Advanced Devices and Architectures

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Abstract

The last chapter of this book is for advanced devices and brand new architectures around FPGAs. Since the basic logic blocks of FPGAs are consisting of LUTs, they are called fine-grained reconfigurable architectures. In contrast, coarse-grained reconfigurable architectures use processing elements to improve the performance per power for computation-centric applications. Dynamic reconfiguration is also easily done in such an architecture, and the configuration data set is called a hardware context. By switching hardware context frequently, they can achieve better usage of semiconductor area. The next part is asynchronous FPGA which can be a breakthrough of high-performance operation with low-power consumption. The handshake mechanism, a key component of such architectures, is explained in detail. 3D implementation is another new trend, while 2.5D is now in commercial use. The last part of this chapter is for activities of optical techniques around FPGAs for drastic improvement I/O and reconfiguration performance.

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References

  1. R. Tessier, K. Pocek, A. DeHon, Reconfigurable computing architectures, in Proceedings of the IEEE, vol. 103, no. 3, pp. 332–351 (March 2015)

    Google Scholar 

  2. K. Masuyama, Y. Fujita, H. Okuhara, H. Amano, A 297MOPS/0.4 mW ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2, in Proceedings of The 10th International Conference on Reconfigurable Computing and FPGAs (ReConFig) (Dec 2015)

    Google Scholar 

  3. J. Yao, Y. Nakashima, N. Devisetti, K. Yoshimura, T. Nakada

    Google Scholar 

  4. X.-P. Ling, H. Amano, WASMII: a data driven computer on a virtual hardware, in IEEE Workshop on FPGAs for Custom Computing Machines, pp. 33–42 (April 1993)

    Google Scholar 

  5. T. Toi, T. Awashima, M. Motomura, H. Amano, Time and space-multiplexed compilation challenge for dynamically reconfigurable processors, in Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 31–39 (Aug 2011)

    Google Scholar 

  6. T.E. Williams, M.E. Dean, D.L. Dill, Efficient self-timing with level-encoded 2-phase dual-rail(ledr), in Proceedings University of California/Santa Cruz Conference Advanced Research, VLSI (1991)

    Google Scholar 

  7. R. Payne, Self-timed FPGA systems, in Proceedings International, Workshop Field Program Logic, Applications (1995)

    Google Scholar 

  8. V. Akella, K. Maheswaran, PGA-STC: programmable gate array for implementing self-timed circuits. Int. J. Electron. 84(3) (1998)

    Google Scholar 

  9. M. Kameyama, Y. Komatsu, M. Hariyama, Anasynchronous high-performance FPGA based on LEDR/four-phase-dual rail hybrid archicture. Proc. 5th Int. Symp. HEART (2014)

    Google Scholar 

  10. R. Manohar, Reconfigurable asynchronous logic, in Proceedings IEEE Custom Integrated, Circuits Conference (2006)

    Google Scholar 

  11. R. Manohar, J. Teifei, An asynchronous dataflow FPGA architecture. IEEE Trans. Comput. 53(11) (2004)

    Google Scholar 

  12. M. Hariyama, M. Kameyama, S. Ishihara, Z. Xie, Evaluation of a self-adaptive voltage control scheme for low-power FPGA. J. Semicond. Tech. Sci. 10(3) (2010)

    Google Scholar 

  13. M. Kameyama, S. Ishihara, M. Hariyama, A low-power FPGA based on autonomous fine-grain power gating. IEEE Trans. VLSI Syst. 19(8) (2011)

    Google Scholar 

  14. Achronix SpeedSter22 HP (2011), http://www.achronix.com/products/speedster22ihp.html

  15. B. Devlin, M. Ikeda, K. Asada, A 65 nm gate-level pipelined self-synchronous FPGA for high performance and variation robus operation. IEEE J. Solid-State Circuits 46(11) (2011)

    Google Scholar 

  16. B. Devlin, M. Ikeda, K. Asada, A gate-level pipelined 2.97 GHz self synchronous FPGA in 65 nm FPGA CMOS. Prof. ASP-DAC (2011)

    Google Scholar 

  17. M. Kameyama, Y. Komatsu, H. Hariyama, An asynchronous high-performance FPGA based on LADR/four-phase-dual-rail hybrid architecture. Proc. HEART (2014)

    Google Scholar 

  18. Y. Tsuchiya, M. Komatsu, H. Hariyama, M. Kameyama, R. Ishihara, Implementation of a low-power FPGA based on synchronous/asynchronous hybrid architecture. IEICE Trans. Electron. E94-C(10) (2011)

    Google Scholar 

  19. A. Bardsley, Implementation balsa handshake circuits. Ph.D. Thesis (Eindhovan Universithy of Technology, 1996)

    Google Scholar 

  20. M. Roncken, R. Saeijs, F. Schalij, K. Berkel, J. Kessels, The VLSI programming language trangram and its translation into handshake circuits, in Proceedings European Conference in Design Automation, EDAC (1991)

    Google Scholar 

  21. M. Kameyama, Y. Komatsu, H. Hariyama, Architecture of an asynchronous FPGA for handshake-component-based design. IEICE Trans. Fund. E88-A(12) (2005)

    Google Scholar 

  22. A.W. Topol, D.C. La Tulipe, L. Shi, D.J. Frank, K. Bernstein, S.E. Steen, A. Kumar, G.U. Singco, A.M. Young, K.W. Guarini, M. Ieong, Three-dimensional integrated circuits. IBM J. Res. Develop. 50(4), 5 (2006)

    Google Scholar 

  23. G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Stucchi, M. Rakowski, I. Debusschere, P. Soussan, W. Dehaene, K. De Meyser, Y. Travaly, E. Beyne, S. Biesmans, B. Swinne, 3D stacked ICs using Cu TSVS and die to wafer hybrid collective bonding. IEEE Int. Electron Dev. Meeting IEDM (2009)

    Google Scholar 

  24. K. Banerjee, S.J. Souri, P. Kapur, K.C. Saraswat, 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and sisytes-on-chip intergration. Proc. IEEE 89(5) (2001)

    Google Scholar 

  25. M. Lin, A. El Gamal, Y.-C. Lu, S. Wong, Performance benefits of monolithically stacked 3-D FPGA. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 26(2) (2007)

    Google Scholar 

  26. R. Le, S. Reda, R. Iris Bahar, High-performance, const-effective heterogeneous 3D FPGA Architectures, in Proceedings the 19th ACM Great Lake Symposium VLSI (2000)

    Google Scholar 

  27. T. Naito, T. Ishida, T. Onoduka, M. Nishigoori, T. Nakayama, Y. Ueno, Y. Ishimoto, A. Suzuki, W. Chung, R. Madurawe, S. Wu, S. Ikeda, H. Oyamatsu, World’s first monolithic 3D-FPGA with ifi SRAM over 90 nm 9 layer Cu CMOS, in Proceedings Symposium VLSI Technology (2010)

    Google Scholar 

  28. Y.Y. Liauw, Z. Zhang, Z. Zhang, W. Kim, A.E. Gamal, S.S. Wong, Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory. ISSCC (2012)

    Google Scholar 

  29. A. Gayasen, V. Narayanan, M. Kandemir, A. Rahman, Designing a 3-D FPGA: switch box architecture and thermal issues. IEEE Trans. VLSI Syst. 16(7) (2008)

    Google Scholar 

  30. F. Furuta, T. Matsumura, K. Osada, M. Aoki, K. Hozawa, K. Takeda, N. Miyamoto, Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/w, 33 Tbps/mm\(^2\). IEEE Trans. VLSI Syst. (2013)

    Google Scholar 

  31. M.J. Alexander, J.P. Cohoon, J.L. Colflesh, J. Karro, G. Robins, Three-dimensional field-programmable gate arrays, in Proceedings of 8th Annual IEEE International ASIC Conference and Exhibit (1995)

    Google Scholar 

  32. S.A. Razavi, M.S. Zamani, K. Bazargan, A tileable switch module architecture for homogeneous 3D FPGAs, in Proceedings IEEE International 3D System Integration (2009)

    Google Scholar 

  33. A. Rahman, S. Das, A.P. Chandrakasan, R. Reif, Wiring requerement and three-dimensional integration technology for field programmable gate arrays. IEEE Trans. VLSI Syst. 11(1) (2003)

    Google Scholar 

  34. C. Ababei, H. Mogal, K. Bazargan, Three-diminsional place and route for FPGAs. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 25(6) (2006)

    Google Scholar 

  35. M. Amagasaki, Y. Takeuchi, Q. Zhao, M. Iiea, M. Kuga, T. Sueyoshi, Architecture exploration of 3D FPGA to minimize internal layer connection, in ACM/IEEE International Conference on 3D Systems Integration (2015)

    Google Scholar 

  36. M.J. Alexander, J.P. Cohoon, J.L. Colflesh, J. Karro, E.L. Peters, G. Robins, Placement and routing for three-dimensional FPGAs, in 4th Canadian Workshop Field Programmable Devices (1996)

    Google Scholar 

  37. M. Lin, A. El Gamal, A routing fabric for monolithically stacked 3D FPGA, in Proceedings ACM/IEEE International Conference on FPGA (2007)

    Google Scholar 

  38. N. Miyamoto, Y. Matsuomto, H. Koike, T. Matsumura, K. Osada, Y. Nakagawa, T. Ohmi, Development of a CAD tool for 3D-FPGAs, in IEEE International Conference on 3D Systems Integration (2010)

    Google Scholar 

  39. Y. Kwon, P. Lajevardi, A.P. Ch, D.E. Troxel, A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool, in Proceedings of SLIP ’05 (2005)

    Google Scholar 

  40. A. Putnam, et al., A reconfigurable fabric for accelerating large-scale datacenter services, in ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp. 13–24 (2014)

    Google Scholar 

  41. The Telecommunications Industry Association (TIA), Electrical characteristics of low voltage differential signaling (LVDS) interface circuits, PN-4584 (May 2000)

    Google Scholar 

  42. National Semiconductor: RSDS Intra-panel Interface Specification (May 2003)

    Google Scholar 

  43. Texas Instruments, mini-LVDS Interface Specification (2003)

    Google Scholar 

  44. Altera Corporation: Stratix IV Device Handbook, vol. 1 (June 2015)

    Google Scholar 

  45. Altera Corporation: Stratix V Device Handbook, vol. 1 (June 2015)

    Google Scholar 

  46. Altera Corporation: High speed board design Ver.4.0, Application Note 75 (Nov 2001)

    Google Scholar 

  47. M. Peng Li, J. Martinez, D. Vaughan, Transferring high-speed data over long distances with combined FPGA and multichannel optical modules (2012)

    Google Scholar 

  48. H. Li, K. Iga, Vertical-cavity surface-emitting laser devices, in Springer Series in Photonics, vol. 6 (2003)

    Google Scholar 

  49. J. Mumbra, D. Psaltis, G. Zhou, X. An, F. Mok, Optically programmable gate array (OPGA). Opt. Comput. (1999)

    Google Scholar 

  50. H. Morita, M. Watanabe, Microelectromechanical configuration of an optically reconfigurable gate array. IEEE J. Quant. Electron. 46(9), 1288–1298 (Sept 2008)

    Google Scholar 

  51. Y. Yamaguchi, M. Watanabe, Liquid crystal holographic configurations for ORGAs. Opt. Comput. 47(28), 4692–4700 (2008)

    Google Scholar 

  52. Y. Yamaji, M. Watanabe, A 4-configuration-context optically reconfigurable gate array with a MEMS interleaving method, in NASA/ESA Conference on Adaptive Hardware and Systems, pp. 172–177 (June 2013)

    Google Scholar 

  53. A. Ogiwara, M. Watanabe, Optical reconfiguration by anisotropic diffraction in holographic polymer-dispersed liquid crystal memory. Appl Opt 51(21), 5168–5188 (July 2012)

    Google Scholar 

  54. H.J. Coufal, D. Psaltis, G.T. Sincerbox, Holographic data storage, in Springer Series in Optical Sciences, vol. 76 (2000)

    Google Scholar 

  55. S.-L.L. Lu, P. Yiannacouras, R. Kassa, M. Konow, T. Suh, An FPGA-based Pentium in a complete desktop system, in ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, pp. 53–59 (2007)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Hokkaido University, Sapporo, Japan

    Masato Motomura

  2. Tohoku University, Sendai, Japan

    Masanori Hariyama

  3. Shizuoka University, Shizuoka, Japan

    Minoru Watanabe

Authors
  1. Masato Motomura
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  2. Masanori Hariyama
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  3. Minoru Watanabe
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Corresponding author

Correspondence to Masanori Hariyama .

Editor information

Editors and Affiliations

  1. Keio University, Yokohama, Japan

    Hideharu Amano

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Motomura, M., Hariyama, M., Watanabe, M. (2018). Advanced Devices and Architectures. In: Amano, H. (eds) Principles and Structures of FPGAs. Springer, Singapore. https://doi.org/10.1007/978-981-13-0824-6_8

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  • DOI: https://doi.org/10.1007/978-981-13-0824-6_8

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  • Print ISBN: 978-981-13-0823-9

  • Online ISBN: 978-981-13-0824-6

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