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Design Methodology

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Principles and Structures of FPGAs

Abstract

A typical misunderstanding is that design automation techniques used in FPGA tools are just subsets or extension of those developed for LSI design tools. In reality, a unique FPGA structure requires original design automation techniques, and they are critical to extract enough performance with a limited resource on an FPGA chip. This chapter introduces them from the viewpoint of CAD (Computer Aided Design) developer. Techniques for technology mapping, clustering, and place and routing are introduced. Then, low power design which has become a critical issue is introduced. Although this chapter includes some expert knowledge, even beginners can understand the specialties and challenges of FPGA tools.

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Notes

  1. 1.

    A Boolean network is a way of expressing a gate level netlist, represented by a valid graph (DAG). Each node is composed of a logic gate or a combination circuit of logic gates, and the directional branch represents an input/output signal.

  2. 2.

    Their place and route tool uses XML from VPR 5.0, but VTR 6.0 extends it so that it can more describe complex structures with a simple notation. The VPR place and route tool is described in the next section.

  3. 3.

    A NP-hard problem is at least equal to or more difficult than the problem belonging to the Non-Deterministic Polynomial Time (NP) class in computational complexity theory. Quadratic Assignment Problem (QAP) is said to be one of particularly difficult problems among NP-hard combinatorial optimization problems.

  4. 4.

    The Simulated Annealing method is a general-purpose stochastic meta-heuristic algorithm. The feature of SA is to accelerate the convergence by decreasing its acceptance probability due to temperature change when trying to escape local solution using randomness.

  5. 5.

    The switching activity has almost the same meaning as the toggle rate (TR). The toggle rate is the number of transitions from the logic value 0 to the logic value 1 of the target node and the transition from the logic value 1 to the logic value 0 per unit time.

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Authors and Affiliations

  1. Kumamoto University, Kumamoto, Japan

    Masahiro Iida

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  1. Masahiro Iida
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Correspondence to Masahiro Iida .

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Editors and Affiliations

  1. Keio University, Yokohama, Japan

    Hideharu Amano

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Iida, M. (2018). Design Methodology. In: Amano, H. (eds) Principles and Structures of FPGAs. Springer, Singapore. https://doi.org/10.1007/978-981-13-0824-6_5

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  • DOI: https://doi.org/10.1007/978-981-13-0824-6_5

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-0823-9

  • Online ISBN: 978-981-13-0824-6

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