Abstract
In this paper, multi-threshold voltage CMOS technique (MTCMOS) is investigated on static random access memory (SRAM) cell. Cell or/and pass transistors with high threshold and various aspect ratios (β) of transistor are presented. This work is focused on stability, power consumption, delay and write-trip point of SRAM cell, which are very important parameters to design any memory circuit. The read, write and hold stability of data is improved by 2.13×, 1.06× and 1.25×, respectively, with new MTCMOS SRAM cells. The read and write power is suppressed by 1.08× and 2.83×, respectively, and the read delay is suppressed by up to 1.96×, and write-trip point is enhanced by 1.03× with proposed MTCMOS SRAM cells compared with conventional 6T SRAM circuit in 70 nm with MTCMOS technique.
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Acknowledgements
We would like to express our regards to M.P. Council of Science & Technology, Bhopal, India, for the finical support under R&D project scheme (No. 1950/CST/R&D/Phy&EnggSc/2015: 27th Aug 2015.0).
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Parihar, P., Gupta, N., Neema, V., Singh, P. (2019). 6T SRAM Cell Design and Investigation for Ultra-Low-Power Application. In: Nath, V., Mandal, J. (eds) Nanoelectronics, Circuits and Communication Systems . Lecture Notes in Electrical Engineering, vol 511. Springer, Singapore. https://doi.org/10.1007/978-981-13-0776-8_49
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DOI: https://doi.org/10.1007/978-981-13-0776-8_49
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