Advertisement

VLSI Floorplanning Using Entropy Based Intelligent Genetic Algorithm

  • Amarbir SinghEmail author
  • Leena Jain
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 805)

Abstract

Very Large-Scale Integrated (VLSI) floorplanning is NP-hard combinatorial optimization problem and it is vital in chip design as it determines the quality of chips. To solve this problem in an effective manner, an intelligent approach based on heuristic placement strategy and entropy based genetic algorithm is proposed in this paper called Entropy Based Intelligent Genetic Algorithm (EBIGA). In the proposed work, concept of entropy is introduced in genetic algorithm in order to resolve the problem of local optimal solution. An integer coding representation is used in this paper which makes the task of representation of modules simple. The experimental results on Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Centre (GSRC) benchmarks demonstrate that EBIGA can achieve the optimal and competitive solutions for both fixed-outline and outline-free floorplans.

Keywords

VLSI floorplanning Entropy Genetic algorithm 

Notes

Acknowledgement

Authors are thankful to the I.K. Gujral Punjab Technical University, Jalandhar for the support and motivation for research.

References

  1. 1.
    Hutcheson, D.G.: Moore's Law: the history and economics of an observation that changed the world. Electrochem. Soc. INTERFACE 14(1), 17–21 (2005)Google Scholar
  2. 2.
    Chen, G., Guo, W., Chen, Y.: A PSO-based intelligent decision algorithm for VLSI floorplanning. Soft Comput. Methodol. Appl. 14(12), 1329–1337 (2009)CrossRefGoogle Scholar
  3. 3.
    Zhou, R., RuCai, G.T.: Applications of entropy in finance: a review. Entropy 15(11), 4909–4931 (2013)MathSciNetCrossRefGoogle Scholar
  4. 4.
    Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-tree representation of non-slicing floorplan and its applications. In: Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, DAC 1999, pp. 268–273. ACM, New York (1999)Google Scholar
  5. 5.
    Wang, T.C., Wong, D.F.: An optimal algorithm for floorplan area optimization. In: Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC 1990, pp. 180–186. ACM, New York (1990)Google Scholar
  6. 6.
    Otten, R.H.: Automatic floorplan design. In: Proceedings of the 19th Design Automation Conference, DAC 1982, pp. 261–267. IEEE Press, Piscataway (1982)Google Scholar
  7. 7.
    Wong, D.F., Liu, C.L.: A new algorithm for floorplan design. In: Proceedings of the 23rd ACM/IEEE Design Automation Conference, DAC 1986, pp. 101–107. IEEE Press, Piscataway (1986)Google Scholar
  8. 8.
    Guo, P.-N., Takahashi, T., Cheng, C.-K.: Floorplanning using a tree representation. IEEE Trans. CAD Integr. Circ. Syst. 20(2), 281–289 (2001)CrossRefGoogle Scholar
  9. 9.
    Chen, G., Guo, W., Cheng, H., Fen, X., Fang, X.: VLSI floorplanning based on particle swarm optimization. In: Proceedings of 3rd International Conference on Intelligent System and Knowledge Engineering, pp. 1020–1025. IEEE (2008)Google Scholar
  10. 10.
    Jain, L., Singh, A.: Non slicing floorplan representations in VLSI floorplanning: a summary. Int. J. Comput. Appl. 71(15), 12–19 (2013)Google Scholar
  11. 11.
    Hong, X.L., Huang, G., Cai, Y.C., Gu, J.C., Dong, S.Q., Cheng, C.K., Gu, J.: Corner block list: an effective and efficient topological representation of non-slicing floorplan. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 8–12. ACM/IEEE (2000)Google Scholar
  12. 12.
    Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. CAD 15(12), 1518–1524 (1996)CrossRefGoogle Scholar
  13. 13.
    Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module packing based on the BSG-structure and IC layout applications. IEEE Trans. CAD 17(6), 519–530 (1998)CrossRefGoogle Scholar
  14. 14.
    Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-tree representation of non-slicing Floorplan and its applications. In: Proceedings of the 36th ACM/IEEE Conference on Design Automation, New Orleans, Louisiana, United States, pp. 268–273 (1999)Google Scholar
  15. 15.
    Lin, J.M., Chang, Y.W.: TCG: a transitive closure graph-based representation for non-slicing floorplans. In: Proceedings of the 38th Design Automation Conference, Las Vegas, USA, pp. 764–769 (2001)Google Scholar
  16. 16.
    Chang, Y.C., Chang, Y.W., Wu, G.M.: B*-tree: a new representation for non-slicing Floorplans. In: Proceedings of the 37th Conference on Design Automation, pp. 458–463. ACM, Los Angeles (2000)Google Scholar
  17. 17.
    Chen, T.-C., Chang, Y.-W.: Modern floorplanning based on B*-Tree and fast simulated annealing. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 25(4), 637–650 (2006)MathSciNetCrossRefGoogle Scholar
  18. 18.
    Gwee, B.H., Lim, M.H.: A GA with heuristic based decoder for IC floorplanning INTEGRATION. VLSI J. 28(2), 157–172 (1999)Google Scholar
  19. 19.
    Kahng, A.B.: Classical floorplanning harmful. In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, pp. 207–213. ACM, New York (2000)Google Scholar
  20. 20.
    Adya, S.N., Markov, I.L.: Fixed—outline floorplanning: enabling hierarchical design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(6), 1120–1135 (2003)CrossRefGoogle Scholar
  21. 21.
    Adya, S.N., Markov, I.L.: Fixed-outline floorplanning through better local search. In: Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, ICCD 2001, pp. 328–334. IEEE Computer Society, Austin (2001)Google Scholar
  22. 22.
    Kang, M., Dai, W.: Arbitrary rectilinear block packing based on sequence pair. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 259–266 (1998)Google Scholar
  23. 23.
    Tang, M., Yao, X.: A memetic algorithm for VLSI floorplanning. IEEE Trans. Syst. Man Cybernet. B Cybernet. 37(1), 62–69 (2007)CrossRefGoogle Scholar
  24. 24.
    Fernando, P., Katkoori, S.: An elitist non-dominated sorting based genetic algorithm for simultaneous area and wirelength minimization in VLSI floorplanning. In: International Conference on VLSI Design, pp. 337–342. IEEE (2008)Google Scholar
  25. 25.
    Rahim, H.A., Rahman, A.A.H. Ab., Andal jayalakshmi, G., Firuz, S.: A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree. In: Proceedings of the International Conference on Computer and Communication Engineering. IEEE (2008)Google Scholar
  26. 26.
    Chen, J., Zhu, W.: A hybrid genetic algorithm for VLSI floorplanning. In: International Conference on Intelligent Computing and Intelligent Systems (ICIS), pp. 128–132. IEEE (2010)Google Scholar
  27. 27.
    kiyota, K., Fuiiyoshi, K.: Simulated annealing search through general structure floorplans using sequence-pair. In: Symposium on Circuits and Systems, Geneva, Switzerland, pp. 77–80. IEEE (2000)Google Scholar
  28. 28.
    Fang, J.-P., Chang, Y.-L., Chen, C.-C., Liang, W.-Y., Hsieh, T.-J., Satria, M.T., Han, C.-C.: A parallel simulated annealing approach for floorplanning in VLSI. In: Hua, A., Chang, S.-L. (eds.) ICA3PP 2009. LNCS, vol. 5574, pp. 291–302. Springer, Heidelberg (2009).  https://doi.org/10.1007/978-3-642-03095-6_29CrossRefGoogle Scholar
  29. 29.
    Anand, S., Saravanasankar, S., Subbaraj, P.: Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem. Comput. Optim. Appl. 52(3), 667–689 (2011)MathSciNetCrossRefGoogle Scholar
  30. 30.
    Chen, J., Zhu, W., Ali, M.M.: Hybrid simulated annealing algorithm for nonslicing VLSI floorplanning. IEEE Trans. Syst. Man Cybernet. Part C Appl. Rev. 41(4), 544–553 (2011)CrossRefGoogle Scholar
  31. 31.
    Chen, Z., Chen, J., Guo, W., Chen, G.: A co-evolutionary multi-objective PSO algorithm for VLSI floorplanning. In: 8th International Conference on Natural Computation (ICNC), pp. 712–728. IEEE (2012)Google Scholar
  32. 32.
    Wang, X.G., Yao, L.S., Gan, J.R.: VLSI floorplanning method based on genetic algorithms. Chin. J. Semiconductors 23, 330–335 (2002)Google Scholar
  33. 33.
    Pang, Y., Cheng, C.K., Yoshimura, T.: An enhanced perturbing algorithm for floorplan design using the O-tree representation. In: Proceedings ISPD, pp. 168–173 (2000)Google Scholar
  34. 34.
    Tang, X., Wong, D.F.: FAST-SP: a fast algorithm for block placement based on sequence pair. In: Proceedings on ASPDAC (2001)Google Scholar
  35. 35.
    Chen, D.-S., Lin, C.-T., Wang, Y.-W., Cheng, C.-H.: Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. Artif. Intell. 20, 821–830 (2007)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.I. K. Gujral Punjab Technical UniversityJalandharIndia
  2. 2.Global Institute of Management and Emerging TechnologiesAmritsarIndia

Personalised recommendations