Jitter and Phase-Noise in High Speed Frequency Synthesizer Using PLL
Jitter happens when data rates increase in high-speed input and output connections for data communications. Characterizing of jitter and measurement is challenge, jitter defined as the misalignment of edges in a sequence of data bits from their ideal positions. Misalignments can result in data errors, and raised bit error rate in digital communication. Tracking these errors over an extended period determines the system stability. Jitter can be due to deterministic and random phenomena, also referred to as systematic and non-systematic respectively. It is worth mentioning that the benefit of jitter is limited to applications using random number generation. There is hardly any other benefit from jitter. Phase noise and jitter are a very important issue when design a phase-locked and delay-locked loops. Different applications may have different emphasis on the jitter specifications. “Cycle-to-cycle” jitter refers to the time difference between two consecutive Cycles of a period signal. A RMS (root mean square) or peak-to-peak value is used to describe a random jitter. According to the noise sources, it can be classified as internal jitters, caused by the building blocks of PLLs and DLLs, and external jitters. Jitters in an Oscillator have been examined for almost half a century and still a hot topic.
KeywordsFrequency synthesizer Jitter noise Modeling and simulation Phase-locked loop Phase noise Synchronization in digital transmission
The researcher would like to thank the Research Center College of Engineering King Saud University, Kingdom of Saudi Arabia for the financial support provided for the research project.
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