Abstract
NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: (1) effective process technology scaling; and (2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to (1) fewer electrons in the flash memory cell floating gate to represent the data; and (2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this chapter, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including (1) cell-to-cell interference mitigation; (2) optimal multi-level cell sensing; (3) error correction using state-of-the-art algorithms and methods; and (4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future.
Keywords
- Solid State Drives (SSD)
- NAND Flash Memory
- Threshold Voltagethreshold Voltage
- Raw Bit Error Rate (RBER)
- Low-density Parity-check (LDPC)
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Notes
- 1.
See Sect. 9.7 for a discussion on the possible types of errors that can be present in DRAM.
- 2.
Each platform has a different combination of SSDs, host controller interfaces, and workloads. The six platforms are described in detail in [174].
- 3.
Or, more precisely, near-optimal, if the read-retry steps are too coarse grained to find the optimal voltage.
- 4.
Note that an LLR message is not the same as the k-bit data message. The data message refers to the actual data stored within the SSD, which, when read, is modeled in information theory as a message that is transmitted across a noisy communication channel. In contrast, an LLR message refers to the updated LLR values for each bit of the codeword that are exchanged between the check nodes and the bit nodes during belief propagation. Thus, there is no relationship between a data message and an LLR message.
- 5.
Note that not all charge trap transistors rely on FN tunneling. Charge trap transistors used for NOR flash memory change their threshold voltage using channel hot electron injection, also known as hot carrier injection [166].
- 6.
One such work will be presented at the June 2018 Sigmetrics conference [301] as this chapter is being sent to print.
- 7.
More detail on our experimental setup, along with a list of all modules and their characteristics, can be found in our original FLY-DRAM paper [37].
References
N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M. Manasse, R. Panigrahy, Design tradeoffs for SSD performance, in USENIX ATC (2008)
A.R. Alameldeen, I. Wagner, Z. Chisthi, W. Wu, C. Wilkerson, S.-L. Lu, Energy-efficient cache design using variable-strength error-correcting codes, in ISCA (2011)
A. Anastasopoulos, A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution, in GLOBECOM (2001)
S.A. Arrhenius, Über die dissociationswärme und den einfluß der temperatur auf den dissociationsgrad der elektrolytae. Z. Phys. Chem. (1889)
A. Athmanathan, M. Stanisavljevic, N. Papandreou, H. Pozidis, E. Eleftheriou, Multilevel-cell phase-change memory: a viable technology. J. Emerg. Sel. Top. Circuits Syst. (2016)
S. Baek, S. Cho, R. Melhem, Refresh now and then. IEEE Trans. Comput. (2014)
F.M. Benelli, How to extend 2D-TLC endurance to 3,000 P/E cycles. in Flash Memory Summit (2015)
E.R. Berlekamp, Nonbinary BCH decoding, in ISIT (1967)
R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, Introduction to flash memory. Proc. IEEE, April 2003
R.C. Bose, D.K. Ray-Chaudhuri, On a class of error correcting binary group codes. Inf. Control (1960)
E. Bosman, K. Razavi, H. Bos, C. Guiffrida, Dedup est machina: memory deduplication as an advanced exploitation vector, in SP (2016)
J.E. Brewer, M. Gill, Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using NVM Devices (Wiley, Hoboken, NJ, USA, 2008)
W. Burleson, O. Mutlu, and M. Tiwari, Who is the major threat to tomorrow’s security? you, the hardware designer, in DAC (2016)
Y. Cai, NAND flash memory: characterization, analysis, modelling, and mechanisms. Ph.D. Dissertation, Carnegie Mellon University, 2012
Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, O. Mutlu, Error characterization, mitigation, and recovery in flash memory based solid-state drives (2017), arXiv:1706.08642
Y. Cai, S. Ghose, E.F. Haratsch, Y. Luo, O. Mutlu, Error characterization, mitigation, and recovery in flash-memory-based solid-state drives. Proc. IEEE, Sept 2017
Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, E.F. Haratsch, Vulnerabilities in MLC NAND flash memory programming: experimental analysis, exploits, and mitigation techniques, in HPCA (2017)
Y. Cai, E.F. Haratsch, M. McCartney, K. Mai, FPGA-based solid-state drive prototyping platform, in FCCM (2011)
Y. Cai, E.F. Haratsch, O. Mutlu, K. Mai, Error patterns in MLC NAND flash memory: measurement, characterization, and analysis, in DATE (2012)
Y. Cai, E.F. Haratsch, O. Mutlu, K. Mai, Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling, in DATE (2013)
Y. Cai, Y. Luo, S. Ghose, E.F. Haratsch, K. Mai, O. Mutlu, Read disturb errors in MLC NAND flash memory: characterization, mitigation, and recovery, in DSN (2015)
Y. Cai, Y. Luo, E.F. Haratsch, K. Mai, O. Mutlu, Data retention in MLC NAND flash memory: characterization, optimization, and recovery, in HPCA (2015)
Y. Cai, O. Mutlu, E.F. Haratsch, K. Mai, Program interference in MLC NAND flash memory: characterization, modeling, and mitigation, in ICCD (2013)
Y. Cai, Y. Wu, N. Chen, E.F. Haratsch, Z. Chen, Systems and methods for latency based data recycling in a solid state memory system, U.S. Patent 9,424,179 (2016)
Y. Cai, Y. Wu, E.F. Haratsch, Hot-read data aggregation and code selection, U.S. Patent Application 14/192,110 (2015)
Y. Cai, Y. Wu, E.F. Haratsch, System to control a width of a programming threshold voltage distribution width when writing hot-read data, U.S. Patent 9,218,885 (2015)
Y. Cai, Y. Wu, E.F. Haratsch, Data recovery once ECC fails to correct the data, U.S. Patent 9,323,607 (2016)
Y. Cai, Y. Wu, E.F. Haratsch, Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes, U.S. Patent 9,419,655 (2016)
Y. Cai, G. Yalcin, O. Mutlu, E.F. Haratsch, A. Cristal, O. Unsal, K. Mai, Flash correct and refresh: retention aware management for increased lifetime, in ICCD (2012)
Y. Cai, G. Yalcin, O. Mutlu, E.F. Haratsch, A. Cristal, O. Unsal, K. Mai, Error analysis and retention-aware error management for NAND flash memory. Intel. Technol. J. (2013)
Y. Cai, G. Yalcin, O. Mutlu, E.F. Haratsch, O. Unsal, A. Cristal, K. Mai, Neighbor cell assisted error correction in MLC NAND flash memories, in SIGMETRICS (2014)
J. Cha, S. Kang, Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices. ETRI J. (2013)
K. Chandrasekar, S. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, K. Goossens, Exploiting expendable process-margins in DRAMs for run-time performance optimization, in DATE (2014)
K.K. Chang, Understanding and improving the latency of DRAM-based memory systems. Ph.D. Dissertation, Carnegie Mellon University, 2017
K.K. Chang, D. Lee, Z. Chishti, A.R. Alameldeen, C. Wilkerson, Y. Kim, O. Mutlu, Improving DRAM performance by parallelizing refreshes with accesses, in HPCA (2014)
K.K. Chang, P.J. Nair, S. Ghose, D. Lee, M.K. Qureshi, O. Mutlu, Low-cost inter-linked subarrays (LISA): enabling fast inter-subarray data movement in DRAM, in HPCA (2016)
K.K. Chang, A. Kashyap, H. Hassan, S. Ghose, K. Hsieh, D. Lee, T. Li, G. Pekhimenko, S. Khan, O. Mutlu, Understanding latency variation in modern DRAM chips: experimental characterization, analysis, and optimization, in SIGMETRICS (2016)
K.K. Chang, A.G. Yaglikci, A. Agrawal, N. Chatterjee, S. Ghose, A. Kashyap, H. Hassan, D. Lee, M. O’Connor, O. Mutlu, Understanding reduced-voltage operation in modern DRAM devices: experimental characterization, analysis, and mechanisms, in SIGMETRICS (2017)
L.-P. Chang, On efficient wear leveling for large-scale flash-memory storage systems, in SAC (2007)
L.-P. Chang, T.-W. Kuo, S.-W. Lo, Real-time garbage collection for flash-memory storage systems of real-time embedded systems (ACM Trans. Embed. Comput, Syst, 2004)
N. Chatterjee, M. Shevgoor, R. Balasubramonian, A. Davis, Z. Fang, R. Illikkal, R. Iyer, Leveraging heterogeneity in DRAM main memories to accelerate critical word access, in MICRO (2012)
C.-L. Chen, High-speed decoding of BCH codes (Corresp.) IEEE Trans. Inf. Theory (1981)
J. Chen, M.P.C. Fossorier, Near optimum universal belief propagation based decoding of low-density parity check codes (IEEE Trans, Commun, 2002)
T.-H. Chen, Y.-Y. Hsiao, Y.-T. Hsing, C.-W. Wu, An adaptive-rate error correction scheme for nand flash memory, in VTS (2009)
Z. Chen, E.F. Haratsch, S. Sankaranarayanan, Y. Wu, Estimating read reference voltage based on disparity and derivative metrics, U.S. Patent 9,417,797 (2016)
R.T. Chien, Cyclic decoding procedures for the Bose-Chaudhuri-Hocquenghem codes IEEE Trans. Inf. Theory (1964)
B. Choi et al., Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D nand flash memory, in VLSIT (2016)
H. Choi, W. Liu, W. Sung, VLSI implementation of BCH error correction for multilevel cell NAND flash memory (IEEE Trans. Very Large Scale Integr, Syst, 2009)
C. Chou, P. Nair, M.K. Qureshi, Reducing refresh power in mobile devices with morphable ECC, in DSN (2015)
C.-C. Chou, A. Jaleel, M.K. Qureshi, CAMEO: a two-level memory organization with capacity of main memory and flexibility of hardware-managed cache, in MICRO (2014)
C.-C. Chou, A. Jaleel, M.K. Qureshi, BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches, in ISCA (2015)
S. Choudhuri, T. Givargis, Deterministic service guarantees for NAND flash using partial block cleaning, in CODES + ISSS (2008)
L. Chua, Memristor–the missing circuit element (IEEE Trans, Circuit Theory, 1971)
T.-S. Chung, D.-J. Park, S. Park, D.-H.L.S.-W. Lee, H.-J. Song, A survey of flash translation layer. J. Syst. Archit. (2009)
R. Codandaramane, Securing the SSDs—NVMe controller encryption, in Flash Memory Summit (2016)
E.T. Cohen, Zero-one balance management in a solid-state disk controller, U.S. Patent 8,839,073 (2014)
E.T. Cohen, Y. Cai, E.F. Haratsch, Y. Wu, Method to dynamically update LLRs in an SSD drive and/or controller, U.S. Patent 9,329,935 (2015)
J. Cooke, The inconvenient truths of NAND flash memory, in Flash Memory Summit (2007)
J. Daemen, V. Rijmen, The Design of Rijndael (Germany, New York, NY, USA, Springer, Berlin, Heidelberg, 2002)
R. Degraeve et al., Analytical percolation model for predicting anomalous charge loss in flash memories (IEEE Trans. Electron, Devices, 2004)
T.J. Dell, A white paper on the benefits of chipkill-correct ECC for PC server main memory IBM Microelectron. Division Tech. Rep. (1997)
P. Desnoyers, Analytic modeling of SSD write performance, in SYSTOR (2012)
C. Dirik, B. Jacob, The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization, in ISCA (2009)
L. Dolecek, Making error correcting codes work for flash memory, in Flash Memory Summit (2014)
B. Eitan, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping, U.S. Patent 5,768,192 (1998)
J. Elliott, J. Jeong, Advancements in SSDs and 3D NAND reshaping storage market Keynote Present. in Flash Memory Summit (2017)
Facebook, Inc., Flashcache. https://github.com/facebookarchive/flashcache
M.P.C. Fossorier, M. Mihaljević, H. Imai, Reduced complexity iterative decoding of low-density parity check codes based on belief propagation (IEEE Trans, Commun, 1999)
R.H. Fowler, L. Nordheim, Electron emission in intense electric fields Proc. R. Soc. A (1928)
A. Fukami, S. Ghose, Y. Luo, Y. Cai, O. Mutlu, Improving the reliability of chip-off forensic analysis of NAND flash memory devices (Digit, Investig, 2017)
E. Gal, S. Toledo, Algorithms and data structures for flash memories (ACM Comput, Surv, 2005)
R.G. Gallager, Low-density parity-check codes (IRE Trans. Inf, Theory, 1962)
R.G. Gallager, Low-Density Parity-Check Codes (MIT Press, Cambridge, MA, USA, 1963)
S. Ghose, H. Lee, J.F. Martínez, Improving memory scheduling via processor-side load criticality information, in ISCA (2013)
L.M. Grupp, A.M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P.H. Siegel, J.K. Wolf, Characterizing flash memory: anomalies, observations, and applications, in MICRO (2009)
D. Gruss, M. Lipp, M. Schwarz, D. Genkin, J. Juffinger, S. O’Connell, W. Schoechl, Y. Yarom, Another flip in the wall of Rowhammer defenses (2017), arXiv:1710.00551
D. Gruss, C. Maurice, S. Mangard, Rowhammer.js: a remote software-induced fault attack in javascript, in DIMVA (2016)
K. Gunnam, LDPC decoding: VLSI architectures and implementations, in Flash Memory Summit (2014)
K.K. Gunnam, G.S. Choi, M.B. Yeary, M. Atiquzzaman, VLSI architectures for layered decoding for irregular LDPC codes of WiMax, in ICC (2007)
A. Gupta, Y. Kim, B. Urgaonkar, DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings, in ASPLOS (2009)
K. Ha, J. Jeong, J. Kim, A read-disturb management technique for high-density NAND flash memory, in APSys (2013)
K. Ha, J. Jeong, J. Kim, An integrated approach for managing read disturbs in high-density NAND flash memory (IEEE Trans. Comput.-Aided Des. Integr, Circuits Syst, 2016)
T. Hamamoto, S. Sugiura, S. Sawada, On the retention time distribution of dynamic random access memory (DRAM) (IEEE Trans. Electron, Devices, 1998)
L. Han, Y. Ryu, K. Yim, CATA: a garbage collection scheme for flash memory file systems, in UIC (2006)
E.F. Haratsch, Controller concepts for 1y/1z nm and 3D NAND flash, in Flash Memory Summit (2015)
E.F. Haratsch, Media management for high density NAND flash memories, in Flash Memory Summit (2016)
H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, O. Mutlu, SoftMC: a flexible and practical open-source infrastructure for enabling experimental DRAM studies, in HPCA (2017)
H. Hassan, G. Pekhimenko, N. Vijaykumar, V. Seshadri, D. Lee, O. Ergin, O. Mutlu, ChargeCache: reducing DRAM latency by exploiting row access locality, in HPCA (2016)
J. Haswell, SSD architectures to ensure security and performance, in Flash Memory Summit (2016)
J. He, S. Kannan, A.C. Arpaci-Dusseau, R.H. Arpaci-Dusseau, The unwritten contract of solid state drives, in EuroSys (2017)
J. Ho, B. Chester, The iPhone 7 and iPhone 7 Plus review: iterating on a flagship, in AnandTech (2016)
A. Hocquenghem, Codes Correcteurs d’Erreurs. Chiffres (1959)
X.-Y. Hu, E. Eleftheriou, R. Haas, I. Iliadis, R. Pletka, Write amplification analysis in flash-based solid state drives, in SYSTOR (2009)
Y. Hu, H. Jiang, D. Feng, L. Tian, H. Luo, S. Zhang, Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity, in ICS (2011)
P. Huang, P. Subedi, X. He, S. He, K. Zhou, FlexECC: partially relaxing ECC of MLC SSD for better cache performance, in USENIX ATC (2014)
A. Hwang, I. Stefanovici, B. Schroeder, Cosmic rays don’t strike twice: understanding the nature of DRAM errors and the implications for system design, in ASPLOS (2012)
D. Ielmini, A.L. Lacaita, D. Mantegazza, Recovery and drift dynamics of resistance and threshold voltages in phase-change memories (IEEE Trans. Electron, Devices, 2007)
J. Im et al., A 128Gb 3b/Cell V-NAND flash memory with 1Gb/s I/O rate, in ISSCC (2015)
Intel Corp., Serial ATA Advanced Host Controller Interface (AHCI) 1.3.1 (2012)
E. Ipek, O. Mutlu, J. F. Martínez, R. Caruana, Self-optimizing memory controllers: a reinforcement learning approach, in ISCA (2008)
C. Isen, L. John, ESKIMO—Energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem, in MICRO (2009)
J. Jang et al., Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory, in VLSIT (2009)
JEDEC Solid State Technology Assn., Solid-State Drive (SSD) Requirements and Endurance Test Method (Publication JEP218, 2010)
JEDEC Solid State Technology Assn., DDR4 SDRAM Standard (Publication JESD79-4A, 2013)
JEDEC Solid State Technology Assn., Failure Mechanisms and Models for Semiconductor Devices (Publication JEP122H, 2016)
J. Jeong, S.S. Hahn, S. Lee, J. Kim, Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling, in FAST (2014)
S. Jeong, K. Lee, S. Lee, S. Son, Y. Won, I/O stack optimization for smartphones, in USENIX ATC (2013)
L. Jiang, Y. Zhang, J. Yang, Mitigating write disturbance in super-dense phase change memories, in DSN (2014)
X. Jiang, N. Madan, L. Zhao, M. Upton, R. Iyer, S. Makineni, D. Newell, D. Solihin, R. Balasubramonian, CHOP: adaptive filter-based DRAM caching for CMP server platforms, in HPCA (2010)
S.J. Johnson, Introducing low-density parity-check codes, http://sigpromu.org/sarah/SJohnsonLDPCintro.pdf
D. Kahng, S.M. Sze, A floating gate and its application to memory devices. Bell Syst. Tech. J. (1967)
D. Kang et al., 7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers, in ISSCC (2016)
J.-U. Kang, H. Jo, J.-S. Kim, J. Lee, A superblock-based flash translation layer for NAND flash memory, in EMSOFT (2006)
U. Kang, H.-S. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, J. Choi, Co-architecting controllers and DRAM to enhance DRAM process scaling, in Memory Forum (2014)
R. Katsumata et al., Pipe-Shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices, in VLSIT (2009)
S. Khan, D. Lee, Y. Kim, A. Alameldeen, C. Wilkerson, O. Mutlu, The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study, in SIGMETRICS (2014)
S. Khan, D. Lee, O. Mutlu, PARBOR: an efficient system-level technique to detect data-dependent failures in DRAM, in DSN (2016)
S. Khan, C. Wilkerson, D. Lee, A.R. Alameldeen, O. Mutlu, A case for memory content-based detection and mitigation of data-dependent failures in DRAM (IEEE Comput. Archit, Lett, 2016)
S. Khan, C. Wilkerson, Z. Wang, A.R. Alameldeen, D. Lee, O. Mutlu, Detecting and mitigating data-dependent DRAM failures by exploiting current memory content, in MICRO (2017)
W.-S. Khwa et al., A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100 \(\times \) for storage-class memory applications, in ISSCC (2016)
C. Kim et al., A 21 nm high performance 64 Gb MLC NAND flash memory with 400 MB/s asynchronous toggle DDR interface (IEEE J, Solid-State Circuits, 2012)
C. Kim et al., A 512 Gb 3b/Cell 64-Stacked WL 3D V-NAND flash memory, in ISSCC (2017)
J. Kim, M. Sullivan, M. Erez, Bamboo ECC: strong, safe, and flexible codes for reliable computer memory, in HPCA (2015)
J. Kim, M. Sullivan, S.-L. Gong, M. Erez, Frugal ECC: efficient and versatile memory error protection through fine-grained compression, in SC (2015)
J.S. Kim, M. Patel, H. Hassan, O. Mutlu, The DRAM latency PUF: quickly evaluating physical unclonable functions by exploiting the latency–reliability tradeoff in modern DRAM devices, in HPCA (2018)
K. Kim, J. Lee, A new investigation of data retention time in truly nanoscaled DRAMs (IEEE Electron, Device Lett, 2009)
N. Kim, J.-H. Jang, Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device. U.S. Patent 8,203,881 (2012)
Y. Kim, Architectural techniques to enhance DRAM scaling. Ph.D. Dissertation, Carnegie Mellon Univ., 2015
Y. Kim, D. Han, O. Mutlu, M. Harchol-Balter, ATLAS: a scalable and high-performance scheduling algorithm for multiple memory controllers, in HPCA (2010)
Y. Kim, O. Mutlu, "Memory Systems," in Computing Handbook, 3rd edn. (CRC Press, Boca Raton, FL, USA, 2014)
Y. Kim, V. Seshadri, D. Lee, J. Liu, O. Mutlu, A case for exploiting subarray-level parallelism (SALP) in DRAM, in ISCA (2012)
Y. Kim, W. Yang, O. Mutlu, Ramulator: a fast and extensible DRAM simulator (IEEE Comput. Archit, Lett, 2016)
Y.S. Kim, D.J. Lee, C.K. Lee, H.K. Choi, S.S. Kim, J.H. Song, D.H. Song, J.-H. Choi, K.-D. Suh, C. Chung, New scaling limitation of the floating gate cell in NAND flash memory, in IRPS (2010)
Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, “Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors, in ISCA (2014)
Y. Kim, M. Papamichael, O. Mutlu, M. Harchol-Balter, Thread cluster memory scheduling: exploiting differences in memory access behavior, in MICRO (2010)
Y. Koh, NAND flash scaling beyond 20 nm, in IMW (2009)
Y. Komori, M. Kido, M. Kito, R. Katsumata, Y. Fukuzumi, H. Tanaka, Y. Nagata, M. Ishiduki, H. Aochi, A. Nitayama, Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device, in IEDM (2008)
E. Kültürsay, M. Kandemir, A. Sivasubramaniam, O. Mutlu, Evaluating STT-RAM as an energy-efficient main memory alternative, in ISPASS (2013)
M. LaPedus, How to make 3D NAND (Semicond, Eng, 2016)
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, Architecting phase change memory as a scalable DRAM alternative, in ISCA (2009)
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, Phase change memory architecture and the quest for scalability. ACM Commun. (2010)
B.C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, D. Burger, Phase-change technology and the future of main memory. IEEE Micro (2010)
C.J. Lee, V. Narasiman, O. Mutlu, Y.N. Patt, Improving memory bank-level parallelism in the presence of prefetching, in MICRO (2009)
D. Lee, Reducing DRAM energy at low cost by exploiting heterogeneity. Ph.D. Dissertation, Carnegie Mellon University, 2016
D. Lee, S. Ghose, G. Pekhimenko, S. Khan, O. Mutlu, Simultaneous multi-layer access: improving 3D-stacked memory bandwidth at low cost. ACM TACO (2016)
D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, O. Mutlu, Design-induced latency variation in modern DRAM chips: characterization, analysis, and latency reduction mechanisms, in SIGMETRICS (2017)
D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, O. Mutlu, Tiered-Latency DRAM: a low latency and low cost DRAM architecture, in HPCA (2013)
D. Lee, L. Subramanian, R. Ausavarungnirun, J. Choi, and O. Mutlu, Decoupled direct memory access: isolating CPU and IO traffic by leveraging a dual-data-port DRAM, in PACT (2015)
D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, O. Mutlu, Adaptive-latency DRAM: optimizing DRAM timing for the common-case, in HPCA (2015)
J.-D. Lee, J.-H. Choi, D. Park, K. Kim, Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells, in IRPS (2003)
J.-D. Lee, S.-H. Hur, J.-D. Choi, Effects of floating-gate interference on NAND flash memory cell operation (IEEE Electron, Device Lett, 2002)
S.-Y. Lee, Limitations of 3D NAND scaling. EE Times (2017)
Y. Lee, H. Yoo, I. Yoo, I.-C. Park, 6.4 Gb/s Multi-threaded BCH encoder and decoder for multi-channel SSD controllers, in ISSCC (2012)
J. Li, K. Zhao, X. Zhang, J. Ma, M. Zhao, T. Zhang, How much can data compressibility help to improve NAND flash memory lifetime? in FAST (2015)
Y. Li, S. Ghose, J. Choi, J. Sun, H. Wang, O. Mutlu, Utility-based hybrid memory management, in CLUSTER (2017)
Y. Li, C. Hsu, K. Oowada, Non-volatile memory and method with improved first pass programming, U.S. Patent 8,811,091 (2014)
J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, O. Mutlu, An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms, in ISCA (2013)
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, RAIDR: retention-aware intelligent DRAM refresh, in ISCA (2012)
S. Liu, K. Pattabiraman, T. Moscibroda, B. Zorn, Flikker: saving DRAM refresh-power through critical data partitioning, in ASPLOS (2011)
W. Liu, J. Rho, W. Sung, Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories, in SIPS (2006)
Y. Luo, Y. Cai, S. Ghose, J. Choi, O. Mutlu, WARM: improving NAND flash memory lifetime with write-hotness aware retention management, in MSST (2015)
Y. Luo, S. Ghose, Y. Cai, E.F. Haratsch, O. Mutlu, Enabling accurate and practical online flash channel modeling for modern MLC NAND flash memory (IEEE J. Sel, Areas Commun, 2016)
Y. Luo, S. Ghose, T. Li, S. Govindan, B. Sharma, B. Kelly, B. Kelly, A. Boroumand, O. Mutlu, Using ECC DRAM to adaptively increase memory capacity (2017), arXiv:1706.08870
Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, O. Mutlu, HeatWatch: improving 3D NAND flash memory device reliability by exploiting self-recovery and temperature awareness, in HPCA (2018)
Y. Luo, S. Govindan, B. Sharma, M. Santaniello, J. Meza, A. Kansal, J. Liu, B. Khessib, K. Vaid, O. Mutlu, Characterizing application memory error vulnerability to optimize datacenter cost via heterogeneous-reliability memory, in DSN (2014)
S. Luryi, A. Kastalsky, A.C. Gossard, R.H. Hendel, Charge injection transistor based on real-space hot-electron transfer (IEEE Trans. Electron, Devices, 1984)
D.J.C. MacKay, R.M. Neal, Near Shannon limit performance of low density parity check codes (IET Electron, Lett, 1997)
A. Maislos, A new era in embedded flash memory, in Flash Memory Summit (2011)
J.A. Mandelman, R.H. Dennard, G.B. Bronner, J.K. DeBrosse, R. Divakaruni, Y. Li, C.J. Radens, Challenges and future directions for the scaling of dynamic random-access memory (DRAM) (IBM J. Res, Develop, 2002)
A. Marelli, R. Micheloni, BCH and LDPC error correction codes for NAND flash memories, in 3D Flash Memories (Springer, Dordrecht, Netherlands, 2016)
J.L. Massey, Shift-register synthesis and BCH decoding (IEEE Trans. Inf, Theory, 1969)
F. Masuoka, M. Momodomi, Y. Iwata, R. Shirota, New ultra high density EPROM and flash EEPROM with NAND structure cell, in IEDM (1987)
J. Meza, Y. Luo, S. Khan, J. Zhao, Y. Xie, O. Mutlu, A case for efficient hardware-software cooperative management of storage and memory, in WEED (2013)
J. Meza, Q. Wu, S. Kumar, O. Mutlu, A large-scale study of flash memory errors in the field, in SIGMETRICS (2015)
J. Meza, Q. Wu, S. Kumar, O. Mutlu, Revisiting memory errors in large-scale production data centers: analysis and modeling of new trends from the field, in DSN (2015)
J. Meza, J. Chang, H. Yoon, O. Mutlu, P. Ranganathan, Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management (IEEE Comput. Archit, Lett, 2012)
R. Micheloni (ed.), 3D Flash Memories (Netherlands, Springer, Netherlands, Dordrecht, 2016)
R. Micheloni, S. Aritome, L. Crippa, Array architectures for 3-D NAND flash memories. Proc. IEEE (2017)
R. Micheloni et al., A 4Gb 2b/Cell NAND flash memory with embedded 5b BCH ECC for 36 MB/s system read throughput, in ISSCC (2006)
Micron Technology, Inc., Memory Management in NAND Flash Arrays, Tech Note TN-29-28, 2005
Micron Technology, Inc., Bad Block Management in NAND Flash Memory, Tech Note TN-29-59, 2011
N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, L.R. Nevill, Bit error rate in NAND flash memories, in IRPS (2008)
K. Mizoguchi, T. Takahashi, S. Aritome, K. Takeuchi, Data-retention characteristics comparison of 2D and 3D TLC NAND flash memories, in IMW (2017)
V. Mohan, Modeling the physical characteristics of NAND flash memory. Ph.D. Dissertation, University of Virginia, 2010
V. Mohan, S. Sankar, S. Gurumurthi, W. Redmond, ReFresh SSDs: enabling high endurance, low cost flash in datacenters. Technical Report No. CS-2012-05 (University of Virginia, 2012)
V. Mohan, T. Siddiqua, S. Gurumurthi, M.R. Stan, How I learned to stop worrying and love flash endurance, in HotStorage (2010)
M. Momodomi, F. Masuoka, R. Shirota, Y. Itoh, K. Ohuchi, R. Kirisawa, Electrically erasable programmable read-only memory with NAND cell structure, U.S. Patent 4,959,812 (1988)
T. Moscibroda, O. Mutlu, Memory performance attacks: denial of memory service in multi-core systems, in USENIX Security (2007)
T. Moscibroda, O. Mutlu, Distributed order scheduling and its application to multi-core DRAM controllers, in PODC (2008)
J. Mukundan, H. Hunter, K.-H. Kim, J. Stuecheli, J.F. Martínez, Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems, in ISCA (2013)
S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, Reducing memory interference in multicore systems via application-aware memory channel partitioning, in MICRO (2011)
O. Mutlu, Memory scaling: a systems architecture perspective, in IMW (2013)
O. Mutlu, The Rowhammer problem and other issues we may face as memory becomes denser, in DATE (2017)
O. Mutlu, T. Moscibroda, Stall-time fair memory access scheduling for chip multiprocessors, in MICRO (2007)
O. Mutlu, T. Moscibroda, Parallelism-aware batch scheduling: enhancing both performance and fairness of shared DRAM systems, in ISCA (2008)
O. Mutlu, L. Subramanian, Research problems and opportunities in memory systems, SUPERFRI (2014)
H. Naeimi, C. Augustine, A. Raychowdhury, S.-L. Lu, J. Tschanz, STT-RAM scaling and retention failure. Intel Technol. J. (2013)
P.J. Nair, V. Sridharan, M.K. Qureshi, XED: exposing on-die error detection information for strong memory reliability, in ISCA (2016)
I. Narayanan, D. Wang, M. Jeon, B. Sharma, L. Caulfield, A. Sivasubramaniam, B. Cutler, J. Liu, B. Khessib, K. Vaid, SSD failures in datacenters: What? When? and Why? in SYSTOR (2016)
K. Naruke, S. Taguchi, M. Wada, Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness, in IEDM (1988)
National Inst. of Standards and Technology, Specification for the Advanced Encryption Standard (AES), FIPS Publication 197, 2001
NVM Express, Inc., NVM Express Specification, Revision 1.3, 2017
S. Ohshima Y. Tanaka, New 3D flash technologies offer both low cost and low power solutions, in Flash Memory Summit (2016)
Openmoko, NAND Bad Blocks, http://wiki.openmoko.org/wiki/NAND_bad_blocks (2012)
Y. Pan, G. Dong, Q. Wu, T. Zhang, Quasi-nonvolatile SSD: trading flash memory nonvolatility to improve storage system performance for enterprise applications, in HPCA (2012)
N. Papandreou, T. Parnell, H. Pozidis, T. Mittelholzer, E. Eleftheriou, C. Camp, T. Griffin, G. Tressler, A. Walls, Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems, in GLSVLSI (2014)
J. Park, J. Jeong, S. Lee, Y. Song, J. Kim, Improving performance and lifetime of NAND storage systems using relaxed program sequence, in DAC (2016)
K.-T. Park et al., A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20nm-node technology, in ISSCC (2011)
K.-T. Park, M. Kang, D. Kim, S.-W. Hwang, B.Y. Choi, Y.-T. Lee, C. Kim, K. Kim, A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories (IEEE J, Solid-State Circuits, 2008)
K. Park et al., Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming. J. Solid-State Circuits (2015)
T. Parnell, NAND flash basics and error characteristics: why do we need smart controllers? in Flash Memory Summit (2016)
T. Parnell, N. Papandreou, T. Mittelholzer, H. Pozidis, Modelling of the threshold voltage distributions of sub-20nm NAND flash memory, in GLOBECOM (2014)
T. Parnell, R. Pletka, NAND flash basics and error characteristics, in Flash Memory Summit (2017)
M. Patel, J.S. Kim, O. Mutlu, The reach profiler (REAPER): enabling the mitigation of DRAM retention failures via profiling at aggressive conditions, in ISCA (2017)
D.A. Patterson, G. Gibson, R.H. Katz, A case for redundant arrays of inexpensive disks (RAID), in SIGMOD (1988)
P. Pavan, R. Bez, P. Olivo, E. Zanoni, Flash memory cells–an overview. Proc. IEEE (1997)
PCI-SIG, PCI Express Base Specification Revision 3.1a, 2015
J. Pearl, Reverend bayes on inference engines: a distributed hierarchical approach, in AAAI (1982)
W.W. Peterson, D.T. Brown, Cyclic codes for error detection (Proc, IRE, 1961)
S. Phadke, S. Narayanasamy, MLP aware heterogeneous memory system, in DATE (2011)
A. Pirovano, A.L. Lacaita, F. Pellizzer, S.A. Kostylev, A. Benvenuti, R. Bez, Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials (IEEE Trans, Electron Devices, 2004)
Z. Qin, Y. Wang, D. Liu, Z. Shao, Y. Guan, MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems, in DAC (2011)
M. Qureshi, D.H. Kim, S. Khan, P. Nair, O. Mutlu, AVATAR: a variable-retention-time (VRT) aware refresh for DRAM systems, in DSN (2015)
M.K. Qureshi, V. Srinivasan, J.A. Rivers, Scalable high performance main memory system using phase-change memory technology, in ISCA (2009)
M.K. Qureshi, G.H. Loh, Fundamental latency trade-off in architecting DRAM caches: outperforming impractical SRAM-tags with a simple and practical design, in MICRO (2012)
L.E. Ramos, E. Gorbatov, R. Bianchini, Page placement in hybrid memory systems, in ICS (2011)
K. Razavi, B. Gras, E. Bosman, B. Preneel, C. Guiffrida, H. Bos, Flip Feng Shui: hammering a needle in the software stack, in USENIX Security (2016)
P.J. Restle, J.W. Park, B.F. Lloyd, DRAM variable retention time, in IEDM (1992)
D. Rollins, A Comparison of Client and Enterprise SSD Data Path Protection (Micron Technology, Inc., 2011)
W. Ryan, S. Lin, Channel Codes: Classical and Modern (Cambridge University Press, Cambridge, UK, 2009)
Samsung Electronics Co., Ltd., Samsung V-NAND Technology (2014), http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf
Samsung Electronics Co., Ltd., Samsung SSD 960 PRO M.2 Data Sheet Rev. 1.1 (2017)
B. Schroeder, R. Lagisetty, A. Merchant, Flash reliability in production: the expected and the unexpected, in FAST (2016)
B. Schroeder, E. Pinheiro, W.-D. Weber, DRAM errors in the wild: a large-scale field study, in SIGMETRICS (2009)
M. Seaborn, T. Dullien, Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges, (Google Project Zero Blog, 2015)
M. Seaborn, T. Dullien, Exploiting the DRAM Rowhammer bug to gain kernel privileges, in BlackHat (2015)
Seagate Technology LLC, Enterprise Performance 15K HDD Data Sheet (2016)
Serial ATA International Organization, Serial ATA Revision 3.3 Specification (2016)
C.E. Shannon, A mathematical theory of communication. Bell Syst. Tech. J. (July 1948)
C.E. Shannon, A mathematical theory of communication. Bell Syst. Tech. J. (Oct 1948)
H. Shim et al., Highly reliable 26nm 64Gb MLC E2NAND (embedded-ECC and enhanced-efficiency) flash memory with MSP (memory signal processing) controller, in VLSIT (2011)
S.-H. Shin et al., A new 3-bit programming algorithm using SLC-to-TLC migration for 8 MB/s high performance TLC NAND flash memory, in VLSIC (2012)
L. Shu, D.J. Costello, Error Control Coding, 2nd edn. (Prentice-Hall, Englewood Cliffs, NJ, USA, 2004)
S. Sills, S. Yasuda, A. Calderoni, C. Cardon, J. Strand, K. Aratani, N. Ramaswamy, Challenges for high-density 16Gb ReRAM with 27nm technology, in VLSIC (2015)
S. Sills, S. Yasuda, J. Strand, A. Calderoni, K. Aratani, A. Johnson, N. Ramaswamy, A copper ReRAM cell for storage class memory applications, in VLSIT (2014)
V. Sridharan, J. Stearley, N. DeBardeleben, S. Blanchard, S. Gurumurthi, Feng Shui of supercomputer memory: positional effects in DRAM and SRAM faults, in SC (2013)
V. Sridharan, N. DeBardeleben, S. Blanchard, K.B. Ferreira, J. Stearley, J. Shalf, S. Gurumurthi, Memory errors in modern systems: the good, the bad, and the ugly, in ASPLOS (2015)
D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor found. Nature (2008)
J. Stuecheli, D. Kaseridis, H.C. Hunter, L.K. John, Elastic refresh: techniques to mitigate refresh penalties in high density memory, in MICRO (2010)
L. Subramanian, D. Lee, V. Seshadri, H. Rastogi, O. Mutlu, The blacklisting memory scheduler: achieving high performance and fairness at low cost, in ICCD (2014)
L. Subramanian, D. Lee, V. Seshadri, H. Rastogi, O. Mutlu, BLISS: balancing performance, fairness and complexity in memory access scheduling (IEEE Trans. Parallel Distrib, Syst, 2016)
L. Subramanian, V. Seshadri, Y. Kim, B. Jaiyen, O. Mutlu, MISE: providing performance predictability and improving fairness in shared main memory systems, in HPCA (2013)
K.-D. Suh et al., A 3.3V 32 Mb NAND Flash memory with incremental step pulse programming scheme. IEEE J. Solid-State Circuits (1995)
K. Takeuchi, S. Satoh, T. Tanaka, K.-I. Imamiya, K. Sakui, A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories (IEEE J, Solid-State Circuits, 1999)
H. Tanaka et al., Bit cost scalable technology with punch and plug process for ultra high density flash memory, in VLSIT (2007)
S. Tanakamaru, C. Hung, A. Esumi, M. Ito, K. Li, K. Takeuchi, 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm, in ISSCC (2011)
L. Tang, Q. Huang, W. Lloyd, S. Kumar, K. Li, RIPQ: advanced photo caching on flash for facebook, in FAST (2015)
R. Tanner, A recursive approach to low complexity codes (IEEE Trans. Inf, Theory, 1981)
Techman Electronics Co., Techman XC100 NVMe SSD, White Paper v1.0, 2016
Toshiba Corp., 3D Flash Memory: Scalable, High Density Storage for Large Capacity Applications (2017), http://www.toshiba.com/taec/adinfo/technologymoves/3d-flash.jsp
A.N. Udipi, N. Muralimanohar, R. Balasubramonian, A. Davis, N.P. Jouppi, LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems, in ISCA (2012)
V. van der Veen, Y. Fratanonio, M. Lindorfer, D. Gruss, C. Maurice, G. Vigna, H. Bos, K. Razavi, C. Guiffrida, Drammer: deterministic Rowhammer attacks on mobile platforms, in CCS (2016)
N. Varnica, LDPC decoding: VLSI architectures and implementations—module 1: LDPC decoding, in Flash Memory Summit (2013)
R.K. Venkatesan, S. Herr, E. Rotenberg, Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM, in HPCA (2006)
C. Wang, W.-F. Wong, Extending the lifetime of NAND flash memory by salvaging bad blocks, in DATE (2012)
J. Wang, K. Vakilinia, T.-Y. Chen, T. Courtade, G. Dong, T. Zhang, H. Shankar, R. Weselk, Enhanced precision through multiple reads for LDPC decoding in flash memories (IEEE J. Sel, Areas Commun, 2014)
W. Wang, T. Xie, D. Zhou, Understanding the impact of threshold voltage on MLC flash memory performance and reliability, in ICS (2014)
H.A.R. Wegener, A.J. Lincoln, H.C. Pao, M.R. O’Connell, R.E. Oleksiak, H. Lawrence, The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device, in IEDM (1967)
J. Werner, A look under the hood at some unique SSD features, in Flash Memory Summit (2010)
C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, S.-L. Lu, Reducing cache power with low-cost, multi-bit error-correcting codes, in ISCA (2010)
M. Willett, Encrypted SSDs: self-encryption versus software solutions, in Flash Memory Summit 2015
E.H. Wilson, M. Jung, M.T. Kandemir, Zombie NAND: resurrecting dead NAND flash for improved SSD longevity, in MASCOTS (2014)
H.-S.P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F.T. Chen, M.-J. Tsai, Metal-Oxide RRAM (Proc, IEEE, 2012)
H.-S.P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, K.E. Goodson, Phase change memory (Proc, IEEE, 2010)
G. Wu, X. He, N. Xie, T. Zhang, DiffECC: improving SSD read performance using differentiated error correction coding schemes, in MASCOTS (2010)
G. Wu, X. He, Reducing SSD read latency via NAND flash program and erase suspension, in FAST (2012)
Y. Wu, Y. Cai, E.F. Haratsch, Fixed point conversion of LLR values based on correlation, U.S. Patent 9,582,361 (2017)
Y. Wu, Y. Cai, E.F. Haratsch, Systems and methods for soft data utilization in a solid state memory system, U.S. Patent 9,201,729 (2017)
Y. Wu, Z. Chen, Y. Cai, E.F. Haratsch, Method of erase state handling in flash channel tracking, U.S. Patent 9,213,599 (2015)
Y. Wu, E.T. Cohen, Optimization of read thresholds for non-volatile memory, U.S. Patent 9,595,320 (2015)
Y. Xiao, X. Zhang, Y. Zhang, R. Teodorescu, One bit flips, one cloud flops: cross-VM Rowhammer attacks and privilege escalation, in USENIX Security (2016)
M. Xu, M. Li, C. Tan, Extended Arrhenius law of time-to-breakdown of ultrathin gate oxides (Appl. Phys, Lett, 2003)
Q. Xu, H. Siyamwala, M. Ghosh, M. Awasthi, T. Suri, Z. Guz, A. Shayesteh, V. Balakrishnan, Performance characterization of hyperscale applications on NVMe SSDs, in SIGMETRICS, (2015)
Q. Xu, H. Siyamwala, M. Ghosh, T. Suri, M. Awasthi, Z. Guz, A. Shayesteh, V. Balakrishnan, Performance analysis of NVMe SSDs and their implication on real world databases, in SYSTOR (2015)
R.-I. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, H. Kume, Analysis of detrap current due to oxide traps to improve flash memory retention, in IRPS (2000)
D.S. Yaney, C.Y. Lu, R.A. Kohler, M.J. Kelly, J.T. Nelson, A meta-stable leakage phenomenon in DRAM charge storage—variable hold time, in IEDM (1987)
J. Yang, High-Efficiency SSD for reliable data storage systems, in Flash Memory Summit (2011)
M.-C. Yang, Y.-M. Chang, C.-W. Tsao, P.-C. Huang, Y.-H. Chang, T.-W. Kuo, Garbage collection and wear leveling for flash memory: past and future, in SMARTCOMP (2014)
N.N. Yang, C. Avila, S. Sprouse, A. Bauche, Systems and methods for read disturb management in non-volatile memory, U.S. Patent 9,245,637 (2015)
H. Yoon, J. Meza, N. Muralimanohar, N.P. Jouppi, O. Mutlu, Efficient data mapping and buffering techniques for multi-level cell phase-change memories. ACM TACO (2014)
H. Yoon, J. Meza, R. Ausavarungnirun, R. Harding, O. Mutlu, Row buffer locality aware caching policies for hybrid memories, in ICCD (2012)
J. H. Yoon, 3D NAND technology: implications to enterprise storage applications, in Flash Memory Summit (2015)
J. H. Yoon, R. Godse, G. Tressler, H. Hunter, 3D-NAND scaling and 3D-SCM—implications to enterprise storage, in Flash Memory Summit (2017)
J.H. Yoon, G.A. Tressler, Advanced flash technology status, scaling trends and implications to enterprise SSD technology enablement, in Flash Memory Summit (2012)
X. Yu, C.J. Hughes, N. Satish, O. Mutlu, S. Devadas, Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation, in MICRO (2017)
W. Zhang, T. Li, Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architectures, in PACT (2009)
Z. Zhang, W. Xiao, N. Park, D.J. Lilja, Memory module-level testing and error behaviors for phase change memory, in ICCD (2012)
K. Zhao, W. Zhao, H. Sun, X. Zhang, N. Zheng, T. Zhang, LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives, in FAST (2013)
P. Zhou, B. Zhao, J. Yang, Y. Zhang, A durable and energy efficient main memory using phase change memory technology, in ISCA (2009)
A. Zuck, S. Toledo, D. Sotnikov, D. Harnik, Compression and SSDs: where and how? in INFLOW (2014)
Y. Luo, S. Ghose, Y. Cai, E.F. Haratsch, O. Mutlu, Improving 3D NAND flash memory lifetime by tolerating early retention loss and process variation, in SIGMETRICS (2018)
Acknowledgements
The authors would like to thank Rino Micheloni for his helpful feedback on earlier drafts of the chapter. They would also like to thank Seagate for their continued dedicated support. Special thanks also goes to our research group SAFARI’s industrial sponsors over the past six years, especially Facebook, Google, Huawei, Intel, Samsung, Seagate, VMware. This work was also partially supported by ETH Zürich, the Intel Science and Technology Center for Cloud Computing, the Data Storage Systems Center at Carnegie Mellon University, and NSF grants 1212962 and 1320531. An earlier, shorter version of this book chapter appears on arxiv.org [15] and in the Proceedings of the IEEE [16].
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Cai, Y., Ghose, S., Haratsch, E.F., Luo, Y., Mutlu, O. (2018). Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery. In: Micheloni, R., Marelli, A., Eshghi, K. (eds) Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Singapore. https://doi.org/10.1007/978-981-13-0599-3_9
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