Abstract
In recent years, network security is the most critical component in information security. In this research, a new simple yet powerful and fast algorithm for AES is proposed. To have a secured data communication on network usage of an iterative symmetric key block, cipher-based AES is proposed widely. AES is implemented by adopting keys of 128, 192, or 256 bits for encryption/decryption of data in block of 128 bits. These include four transformations in AES: substitute bytes, shift rows, mix columns, and add round key. Here in this approach, parallel transformative method in these transformations mainly in mix columns is proposed. This research mainly focused on the designing of AES according to 192-bit key length in the Verilog language and implementation of it in Virtex6 ML605 FPGA evaluation platform using Xilinx ISE 14.4. To enhance the speed of operation of the algorithm, we followed parallel transformative approach, which achieved throughput of 5565.2173 Mbps with maximum frequency 564.972 MHz in latency of about 13 clock cycles.
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Acknowledgements
We thank Abhijth R, Infosys, Mysuru, India, for the extended support in the preparation of this document.
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Prasada, P., Sathisha, Pinto, A.P., Ranjith, H.D. (2019). FPGA Implementation of Parallel Transformative Approach in AES Algorithm. In: Fong, S., Akashe, S., Mahalle, P. (eds) Information and Communication Technology for Competitive Strategies. Lecture Notes in Networks and Systems, vol 40. Springer, Singapore. https://doi.org/10.1007/978-981-13-0586-3_34
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DOI: https://doi.org/10.1007/978-981-13-0586-3_34
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