Hardware Architecture of Reconfigurable Cryptographic Processors
The hardware architecture of reconfigurable cryptographic processors is the customization of the generic reconfigurable computing architecture in the cryptographic field. On the basis of the generic architecture described in Sect. 1.4.1, designers need to optimize each concrete structure and parameter involved in the architecture framework in the cryptographic field. Different from the hardware architecture design of traditional cryptographic processors, i.e., the hardwired design of the data flow diagram for a single cipher algorithm in ASIC and the design of extended instruction set for specific operators and functions of cipher algorithm in ISAP, the hardware design of reconfigurable cryptographic processors shall integrate features of multiple cipher algorithms to implement the flexible and efficient reconfigurable datapath and reconfigurable controller. The reconfigurable computing unit, interconnection networks, heterogeneous module, data storage, configuration control method, configuration information organization, and storage are designed on the basis of common features of cipher algorithms. This chapter summarizes the basic design methods for the hardware architecture of reconfigurable cryptographic processors from the aspects of reconfigurable datapath and reconfigurable controller, thus helping designers analyze how to perform reasonable architecture designs based on a specified demand.
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