FOWLP: Chip-First and Die Face-Up

Chapter

Abstract

The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are presented in this chapter. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm × 10 mm × 150 µm) and test package (13.47 mm × 13.47 mm), and three redistribution layers (RDLs) with the smallest line width/spacing = 5 µm/5 µm. The FOWLP test package on a six-layer printed circuit board (PCB) is subjected to thermal cycling and drop tests. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.

References

  1. 1.
    Lau, J.H., C. Wong, J. Price, and W. Nakayama. 1998. Electronic Packaging. New York: McGraw-Hill Book Company.Google Scholar
  2. 2.
    Kauffman, J.E. 1969. Method of Packaging Integrated Circuits. US Patent 3,436,810, Filed on July 17, 1967, Patented on April 8, 1969.Google Scholar
  3. 3.
    Lin, P.T., M.B. McShane, and H.P. Wilson. 1993. Semiconductor Device Having a Pad Array Carrier Package. US Patent 5,216,278, Filed on March 2, 1992, Patented on June 1, 1993.Google Scholar
  4. 4.
    Elenius, P., and H. Hollack. 2001. Method for Forming Chip Scale Package. US Patent 6,287,893, Filed on July 13, 1998, Patented on September 11, 2001.Google Scholar
  5. 5.
    Lau, J.H., and R.S.-W. Lee. 1999. Chip Scale Package. New York: McGraw-Hill Book Company.Google Scholar
  6. 6.
    Hedler, H., T. Meyer, and B. Vasquez. 2004. Transfer Wafer Level Packaging. US Patent 6,727,576, Filed on October 31, 2001, Patented on April 27, 2004.Google Scholar
  7. 7.
    Brunnbauer, M., et al. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In Proceedings of IEEE/ECTC, May 2006, 547–551.Google Scholar
  8. 8.
    Meyer, T., G. Ofner, S. Bradl, M. Brunnbauer, and R. Hagen. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In Proceedings of IEEE/EPTC, December 2006, W.1–5.Google Scholar
  9. 9.
    Lau, J.H. 2016. Patent Issues of Embedded Fan-Out Wafer/Panel Level Packaging. In Proceedings of IEEE/Semiconductor Technology International Conference, March 2016, 1–7.Google Scholar
  10. 10.
    Lau, J.H. 2013. Through-Silicon Via (TSV) for 3D Integration. New York: McGraw-Hill Book Company.Google Scholar
  11. 11.
    Lau, J.H. 2016. 3D IC Integration and Packaging. New York: McGraw-Hill Book Company.Google Scholar
  12. 12.
    Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20: 38–44.Google Scholar
  13. 13.
    Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, and M. Kawano. 2010. Fan-Out Wafer-Level Packaging with Highly Flexible Design Capabilities. In IEEE/ESTC Proceedings, 2010, 1–6.Google Scholar
  14. 14.
    Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, H. Kobayashi, Y. Kurita, and M. Kawano. 2011. System in Wafer-Level Package Technology with RDL-First Process. In IEEE/ECTC Proceedings, 2011, 59–64.Google Scholar
  15. 15.
    Brunnbauer, M., E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In IEEE/ECTC Proceedings, 2006, 547–551.Google Scholar
  16. 16.
    Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In IEEE/EPTC Proceedings, 2006, 1–5.Google Scholar
  17. 17.
    Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel. 2007. The Redistributed Chip Package: A Breakthrough for Advanced Packaging. In Proceedings of IEEE/ECTC, 2007, 286–291.Google Scholar
  18. 18.
    Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In IEEE/ECTC Proceedings, 2012, 1250–1254.Google Scholar
  19. 19.
    Yoon, S., P. Tang, R. Emigh, Y. Lin, P. Marimuthu, and R. Pendse. 2013. Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions. In IEEE/ECTC Proceedings, 2013, 1855–1860.Google Scholar
  20. 20.
    Braun, T., K.-F. Becker, S. Voges, J. Bauer, R. Kahle, V. Bader, T. Thomas, R. Aschenbrenner, and K.-D. Lang. 2014. 24”×18” Fan-out Panel Level Packing. In IEEE/ECTC Proceedings, 2014, 940–946.Google Scholar
  21. 21.
    Sharma, G., S. Vempati, A. Kumar, N. Su, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J.H. Lau. 2011. Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies. In IEEE/ECTC Proceedings, 2009, 1537–1543. Also, IEEE Transactions on CPMT 1 (5): 52–59.Google Scholar
  22. 22.
    Lim, Y., S. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. Thaw, S. Gaurav, T. Lim, S. Liu, V. Kripesh, and J.H. Lau. 2010. Demonstration of High Quality and Low Loss Millimeter Wave Passives on Embedded Wafer Level Packaging Platform (EMWLP). In IEEE/ECTC Proceedings, 2009, 508–515. Also, IEEE Transactions on Advanced Packaging 33: 1061–1071.Google Scholar
  23. 23.
    Yu, D. 2014. Wafer-Level-System-Integration (WLSI) Technologies for 2D and 3D System-in-Package. In SEMIEUROPE 2014.Google Scholar
  24. 24.
    Lin, J.C., J.P. Hung, N.W. Liu, Y.C. Mao, W.T. Shih, and T.H. Tung. 2015. Packaged Semiconductor Device with a Molding Compound and a Method of Forming the Same. US Patent 9,000,584, Filed on December 28, 2011, Patented on April 7, 2015.Google Scholar
  25. 25.
    Tseng, C., C. Liu, C. Wu, D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, 2016, 1–6.Google Scholar
  26. 26.
    Hsieh, C., C. Wu, and D. Yu. 2016. Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1430–1438.Google Scholar
  27. 27.
    Lau, J.H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, M. Li, J. Hao, Y. Cheung, Z. Li, K. Tan, R. Beica, T. Taylor, C.T. Lo, H. Yang, Y. Chen, S. Lim, N.C. Lee, J. Ran, X. Cao, S. Koh, and Q. Young. 2017. Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging. In IEEE/ECTC Proceedings, 2017, 595–602. Also, IEEE Transactions on CPMT 7 (10): 1729–1938 (October 2017).Google Scholar
  28. 28.
    Lau, J.H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al. 2017. Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs). In IMAPS Proceedings, October 2017, 576–583. Also, IMAPS Transactions. Journal of Microelectronics and Electronic Packaging 123–131 (October 2017).Google Scholar
  29. 29.
    M. Li, Q. Li, J.H. Lau, N. Fan, E. Kuah, K. Wu, et al. 2017. Characterizations of Fan-Out Wafer-Level Packaging. In IMAPS Proceedings, October 2017, 557–562.Google Scholar
  30. 30.
    Hua, X., H. Xu, Z. Li Zhang, D. Chen, K. Tan, J.H. Lau, et al. 2017. Development of Chip-First and Die-Up Fan-Out Wafer-Level Packaging. In IEEE/EPTC Proceedings, December 2017, S23_1-6.Google Scholar
  31. 31.
    Lau, J.H., M. Li, M. Li, I. Xu, T. Chen, Z. Li, K. Tan, et al. 2018. Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging. To be published in IEEE Transactions on CPMT.Google Scholar
  32. 32.
    Lau, J.H., M. Li, Y. Lei, M. Li, X. Qing, C. Zhong, et al. 2018. Reliability of Fan-Out Wafer-Level Packaging (FOWLP) with Large Chips and Multiple Re-Distributed Layers (RDLs). In IEEE/ECTC Proceedings, May 2018.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

Personalised recommendations