Advertisement

Embedded Chip Packaging

  • John H. Lau
Chapter

Abstract

There are many kinds of embedded chip packaging. For example, chips are embedded in epoxy molding compound (EMC), chips are embedded in rigid laminated substrates, chips are embedded in flexible polyimide substrates, chips are embedded in silicon substrates, and chips are embedded in glass substrates. Usually, chips embedded in rigid and flexible laminated/polyimide substrates are in a panel format. In this chapter, except the chips embedded in EMC (which are the focus and will be discussed all over in this book), all the others are briefly mentioned.

References

  1. 1.
    Brunnbauer, M., E. Fürgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In Proceedings of IEEE/ECTC, May 2006, 547–551.Google Scholar
  2. 2.
    Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In Proceedings of IEEE/EPTC, Singapore, December 2006, 1–5.Google Scholar
  3. 3.
    Meyer, T., G. Ofner, S. Bradl, M. Brunnbauer, and R. Hagen. 2008. Embedded Wafer Level Ball Grid Array (eWLB). In Proceedings of IEEE/EPTC, Singapore, December 2008, 994–998.Google Scholar
  4. 4.
    Brunnbauer, M., T. Meyer, G. Ofner, K. Mueller, and R. Hagen. 2008. Embedded Wafer Level Ball Grid Array (eWLB). In Proceedings of IEEE/IEMTS, 2008, 1–6.Google Scholar
  5. 5.
    Pressel, K., G. Beer, T. Meyer, M. Wojnowski, M. Fink, G. Ofner, and B. Römer. 2010. Embedded Wafer Level Ball Grid Array (eWLB) Technology for System Integration. In Proceedings of Japan IEEE/CPMT Symposium, 2010, 1–4.Google Scholar
  6. 6.
    Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In Proceedings of IEEE/ECTC, May 2012, 1250–1254.Google Scholar
  7. 7.
    Jin, Y., J. Teysseyrex, X. Baraton, S. Yoon, Y. Lin, P. Marimuthu. 2011. Development of Next General eWLB (Embedded Wafer Level BGA) Technology. In Proceedings of IWLPC, San Jose, CA, November 2011, 7.1–7.7.Google Scholar
  8. 8.
    Yoon, S., P. Tang, R. Emigh, Y. Lin, P. C. Marimuthu, and R. Pendse. 2013. Fanout Flipchip eWLB (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions. In Proceedings of IEEE/ECTC, Las Vegas, NV, May 2013, 1855–1860.Google Scholar
  9. 9.
    Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel. 2007. The Redistributed Chip Package: A Breakthrough for Advanced Packaging. In Proceedings of IEEE/ECTC, May 2007, 286–291.Google Scholar
  10. 10.
    Hayes, S., N. Chhabra, T. Duong, Z. Gong, D. Mitchell, and J. Wright. 2011. System-in-Package Opportunities with the Redistributed Chip Package (RCP). In Proceedings of IWLPC, November 2011, 10.1–10.7.Google Scholar
  11. 11.
    Sharma, G., V. Rao, A. Kumar, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J.H. Lau. 2011. Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages. IEEE Transactions on CPMT 1 (5): 52–59.Google Scholar
  12. 12.
    Sharma, G., S. Vempati, A. Kumar, N. Su, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J. H. Lau. 2009. Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies. In IEEE/ECTC Proceedings, San Diego, CA, May 2009, 1537–1543.Google Scholar
  13. 13.
    Lim, Y., X. Xiao, R. Vempati, S. Nandar, K. Aditya, S. Gaurav, T. Lim, V. Kripesh, J. Shi, J.H. Lau, and S. Liu. 2010. High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP). IEEE Transactions on Advanced Packaging 33: 1061–1071.CrossRefGoogle Scholar
  14. 14.
    Lim, Y., S. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. Thaw, S. Gaurav, T. Lim, S. Liu, V. Kripesh, and J. H. Lau. 2009. Demonstration of High Quality and Low Loss Millimeter Wave Passives on Embedded Wafer Level Packaging Platform (EMWLP). In IEEE/ECTC Proceedings, San Diego, CA, May 2009, 508–515.Google Scholar
  15. 15.
    Kripesh, V., V. Rao, A. Kumar, G. Sharma, K. Houe, X. Zhang, K. Mong, N. Khan, and J. H. Lau. 2008. Design and Development of a Multi-Die Embedded Micro Wafer Level Package. In IEEE Proceedings of IEEE/ECTC, Orlando, FL, May 2008, 1544–1549.Google Scholar
  16. 16.
    Khong, C., A. Kumar, X. Zhang, S. Gaurav, S. Vempati, V. Kripesh, J. H. Lau, and D. Kwong. 2009. A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package. In IEEE/ECTC Proceedings, San Diego, CA, May 2009, 535–541.Google Scholar
  17. 17.
    Kumar, A., D. Xia, V. Sekhar, S. Lim, C. Keng, S. Gaurav, S. Vempati, V. Kripesh, J. H. Lau, and D. Kwong. 2009. Wafer Level Embedding Technology for 3D Wafer Level Embedded Package. In IEEE/ECTC Proceedings, San Diego, CA, May 2009, 1289–1296.Google Scholar
  18. 18.
    Texas Instruments. 2011. Design SUMMARY for MicroSiP™-Enabled TPS8267xSiP. Dallas, TX, First Quarter.Google Scholar
  19. 19.
    Itoi, K., M. Okamoto, Y. Sano, N. Ueta, S. Okude, O. Nakao, T. Tessier, S. Sivaswamy, and G. Stout. 2011. Laminate Based Fan-Out Embedded Die Packaging Using Polyimide Multilayer Wiring Boards. In Proceedings of IWLPC, San Jose, CA, November 2011, 7.8–7.14.Google Scholar
  20. 20.
    Munakata, K., N. Ueta, M. Okamoto, K. Onodera, K. Itoi, S. Okude, O. Nakao, J. Aday, and T. Tessier. 2013. Polyimede PCB Embedded with Two Dies in Stacked Configuration. In Proceedings of IWLPC, San Jose, CA, November 2013, 5.1–5.6.Google Scholar
  21. 21.
    Kelkar, A., V. Sridharan, K. Tran, K. Ikeuchi, A. Srivastava, V. Khandekar, and R. Agrawal. 2016. Novel Mold-free Fan-out Wafer Level Package using Silicon Wafer. In IMAPS proceedings on International Symposium on Microelectronics, October 2016, 410–414.Google Scholar
  22. 22.
    Tran, K., A. Samoilov, P. Parvarndeh, and A. Kelkar. 2013. Fan-Out and Heterogeneous Packaging of Electronic Components. US2014/0252655 A1, filed on June 28, 2013.Google Scholar
  23. 23.
    JEDEC Standard. JESD22-A104, Temperature Cycling, 2005.Google Scholar
  24. 24.
    Lau, J.H. 2011. Reliability of RoHS Compliant 2D and 3D Interconnects. New York: McGraw-Hill Book Company.Google Scholar
  25. 25.
    Shi, T., C. Buch,V. Smet, Y. Sato, L. Parthier, F. Wei, C. Lee, V. Sundaram, and R. Tummala. 2017. First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration. In IEEE/ECTC Proceedings, May 2017, 41–46.Google Scholar
  26. 26.
    Buch, C., D. Struk, K. Wolter, P. Hesketh, V. Sundaram, and R. Tummala. 2017. Design and Demonstration of Highly Miniaturized, Low Cost Panel Level Glass Package for MEMS Sensors. In IEEE/ECTC Proceedings, May 2017, 1088–1097.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

Personalised recommendations