Skip to main content
SpringerLink
Log in

Flip Chip Technology Versus FOWLP

  • Chapter
  • First Online:
Fan-Out Wafer-Level Packaging

Abstract

In this chapter, a flip chip is defined (Lau in Flip Chip Technologies. McGraw-Hill, New York, 1996 [1]; Lau in Low Cost Flip Chip Technologies. McGraw-Hill, New York, 2000 [2]; Lau et al. in Electronic Packaging. McGraw-Hill, New York, 1998 [3]; Lau in Electronic Manufacturing. McGraw-Hill, New York, 2003 [4]) as a chip attached to the pads of a substrate or another chip with various interconnect materials (e.g., Sn–Pb, Cu, Au, Ag, Ni, In, and isotropic or anisotropic conductive adhesives) and methods [e.g., mass reflow and thermocompression bonding (TCB)], as long as the chip surface (active area or I/O side) is facing the substrate or another chip as shown in Fig. 2.1.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 159.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Lau, J.H. (ed.). 1996. Flip Chip Technologies. New York: McGraw-Hill.

    Google Scholar 

  2. Lau, J.H. 2000. Low Cost Flip Chip Technologies. New York: McGraw-Hill.

    Google Scholar 

  3. Lau, J.H., C. Wong, J. Prince, and W. Nakayama. 1998. Electronic Packaging. New York: McGraw-Hill.

    Google Scholar 

  4. Lau, J.H., N. Lee, C. Wong, and R. Lee. 2003. Electronic Manufacturing. New York: McGraw-Hill.

    Google Scholar 

  5. Davis, E., W. Harding, R. Schwartz, and J. Corning. 1964. Solid Logic Technology: Versatile, High Performance Microelectronics. IBM Journal of Research and Development 8 (2): 102–114.

    Article  Google Scholar 

  6. Totta, P., and R. Sopher. 1969. SLT Device Metallurgy and Its Monolithic Extension. IBM Journal of Research and Development 13 (3): 226–238.

    Article  Google Scholar 

  7. Lau, J.H. 2016. 3D IC Integration and Packaging. New York: McGraw-Hill.

    Google Scholar 

  8. Lau, J.H. 2013. Through-Silicon Vias for 3D Integration. New York: McGraw-Hill.

    Google Scholar 

  9. Lau, J.H. 2011. Reliability of RoHS-Compliant 2D and 3D IC Interconnects. New York: McGraw-Hill.

    Google Scholar 

  10. Lau, J.H., C. Lee, C. Premachandran, and A. Yu. 2010. Advanced MEMS Packaging. New York: McGraw-Hill.

    Google Scholar 

  11. Lim, S., V. Rao, W. Hnin, W. Ching, V. Kripesh, C. Lee, J.H. Lau, J. Milla, and A. Fenner. 2010. Process Development and Reliability of Microbumps. IEEE Transactions on CPMT 33 (4): 747–753.

    Google Scholar 

  12. Sutanto, J. 2012. POSSUMTM Die Design as a Low Cost 3D Packaging Alternative. 3D Packag 25, 16–18.

    Google Scholar 

  13. Lau, J.H. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19 (6): 42–46.

    Google Scholar 

  14. Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20 (3): 38–44.

    Google Scholar 

  15. Lau, J.H., T. Chung, R. Lee, C. Chang, and C. Chen. 1999. A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP). In Chip Scale International Conference, San Jose, CA, September 14–15, 1999, H1–8.

    Google Scholar 

  16. Elenius, P., and H. Yang. 1998. The Ultra CSP Wafer-Scale Package. In High Density Interconnect Conference and Expo, Tempe, AZ, September 15–16, 1998, 36–40.

    Google Scholar 

  17. Lau, J.H., and S.W.R. Lee. 1999. Chip Scale Package. New York: McGraw-Hill.

    Google Scholar 

  18. Lau, J.H., and Y. Pao. 1997. Solder Joint Reliability of BGA, CSP, and Flip Chip Assemblies. New York: McGraw-Hill.

    Google Scholar 

  19. Lau, J.H., and C. Chang. 2000. Taguchi Design of Experiment for Wafer Bumping by Stencil Printing. IEEE Transactions on Electronics Packaging Manufacturing 21 (3): 219–225.

    Article  Google Scholar 

  20. Elenius, P. 1998. Flip Chip Bumping for IC Packaging Contractors. In NEPCON West Conference, Anaheim, CA, March 3–5, 1998, 1403–1407.

    Google Scholar 

  21. Elenius, P., J. Leal, J. Ney, D. Stepniak, and S. Yeh. 1999. Recent Advances in Flip Chip Wafer Bumping Using Solder Paste Technology. In IEEE 49th Electronic Components and Technology Conference, San Diego, CA, June 1–4, 1999, 260–265.

    Google Scholar 

  22. Li, L., S. Wiegele, P. Thompson, and R. Lee. 1998. Stencil Printing Process Development for Low Cost Flip Chip Interconnect. In IEEE 48th Electronic Components and Technology Conference, Seattle, WA, May 25–28, 1998, 421–426.

    Google Scholar 

  23. Wiegele, S., P. Thompson, R. Lee, and E. Ramsland. 1998. Reliability and Process Characterization of Electroless Nickel-Gold/Solder Flip Chip Interconnect Technology. In 48th Electronic Components and Technology Conference, Seattle, WA, May 25–28, 1998, 861–866.

    Google Scholar 

  24. Kloeser, J., K. Heinricht, E. Jung, L. Lauter, A. Ostmann, R. Aschenbrenner, and H. Reichl. 1998. Low Cost Bumping by Stencil Printing: Process Qualification for 200 mm Pitch. In International Symposium on Microelectronics, San Diego, CA, November 1–4, 1998, 288–297.

    Google Scholar 

  25. Cho, M., S. Kang, Y. Kwon, D. Jang, and N. Kim. 1999. Flip-Chip Bonding on PCB With Electroless Ni-Au and Stencil Printing Solder Bump. In SMTA International Conference, San Jose, CA, September 12–16, 1999, 159–164.

    Google Scholar 

  26. Love, D., L. Moresco, W. Chou, D. Horine, C. Wong, and S. Eilin. 1994. Wire Interconnect Structures for Connecting an Integrated Circuit to a Substrate. U.S. Patent No. 5,334,804, filed November 17, 1992 and issued August 2, 1994.

    Google Scholar 

  27. Tung, F. 2003. Pillar Connections for Semiconductor Chips and Method of Manufacture. U.S. Patent No. 6,578,754, filed April 27, 2000 and issued June 17, 2003.

    Google Scholar 

  28. Tung, F. 2004. Pillar Connections for Semiconductor Chips and Method of Manufacture. U.S. Patent No. 6,681,982, filed June 12, 2002 and issued January 27, 2004.

    Google Scholar 

  29. Cappo, F., J. Milliken, and J. Mosley. 1991. Highly Manufacturable Multi-Layered Ceramic Surface Mounted Package. In 11th IEEE/CHMT International Electronic Manufacturing Technology Symposium, San Francisco, CA, September 16–18, 1991, 424–428.

    Google Scholar 

  30. Banks, D., T. Burnette, R. Gerke, E. Mammo, and S. Mattay. 1994. Reliability Comparison of Two Metallurgies for Ceramic Ball Grid Array. In International Conference and Exhibition on Multichip Modules, Denver, CO, April 13–15, 1994, 529–534.

    Google Scholar 

  31. Sigliano, R., and K. Gaughan. 1992. Ceramic Material Options for MCM’s. In 1st International Conference on Multichip Modules, Denver, CO, April 1–3, 1992, 291–299.

    Google Scholar 

  32. Sigliano, R. 1995. Ceramic Substrates for Ball Grid Array Packages. In Ball Grid Array Technology, ed. J. H. Lau, 65–92. New York: McGraw-Hill.

    Google Scholar 

  33. Lau, J.H., and W. Dauksher. 2005. Reliability of an 1657CCGA (Ceramic Column Grid Array) Package With 96.5Sn3.9Ag0.6Cu Lead-Free Solder Paste on PCBs (Printed Circuit Boards). ASME Journal of Electronic Packaging 127 (2): 96–105.

    Article  Google Scholar 

  34. Lau, J.H., T. Castello, D. Shangguan, W. Dauksher, J. Smetana, R. Horsley, D. Love, I. Menis, and B. Sullivan. 2007. Failure Analysis of Lead-Free Solder Joints of an 1657CCGA (Ceramic Column Grid Array) Package. IMAPS Transactions on Journal of Microelectronics and Electronic Packaging 4 (3): 189–213.

    Google Scholar 

  35. Tsukada, Y., S. Tsuchida, and Y. Mashimoto. 1992. Surface Laminar Circuit Packaging. In 42nd IEEE Electronic and Components Technology Conference, San Diego, CA, May 18–20, 1992, 22–27.

    Google Scholar 

  36. Tsukada, Y., and S. Tsuchida. 1992. Surface Laminar Circuit, a Low Cost High Density Printed Circuit Board. In Surface Mount International Conference, San Jose, CA, August 27–29, 1992, 537–542.

    Google Scholar 

  37. Tsukada, Y. 1994. Solder Bumped Flip Chip Attach on SLC Board and Multichip Module. In Chip on Board Technologies for Multichip Modules, ed. J. H. Lau, 410–443. New York: Van Nostrand Reinhold.

    Google Scholar 

  38. Tsukada, Y., Y. Maeda, and K. Yamanaka. 1993. A Novel Solution for MCM-L Utilizing Surface Laminar Circuit and Flip Chip Attach Technology. In Proceedings of 2nd International Conference on Multichip Modules, April 1993, 252–259.

    Google Scholar 

  39. Lau, J.H., and S.W.R. Lee. 2001. Microvias for Low Cost, High Density Interconnects. New York: McGraw-Hill.

    Google Scholar 

  40. Gonzalez, C., R. Wessel, and S. Padlewski. 1999. Epoxy-Based Aqueous Processable Photo Dielectric Dry Film and Conductive ViaPlug for PCB Build-Up and IC Packaging. IEEE Transactions on Advanced Packaging 22 (3): 385–390.

    Article  Google Scholar 

  41. Burgess, L., and P. Madden. 1998. Blind Vias in SMD Pads. Printed Circuit Fabrication 21 (1): 28–29.

    Google Scholar 

  42. Castro, A. 1997. Chip Carrier Package Constructions Made Easier with Dry Film Photo Dielectric. In Proceedings from IPC Works, October 1997, S01-5-1.

    Google Scholar 

  43. Nargi-Toth, K., and P. Gandhi. 1998. Manufacturing Methodologies for High Density Interconnect Structures (HDIS). In CSI Technical Symposium, September 1998, 63–70.

    Google Scholar 

  44. Noddin, D., E. Swenson, and Y. Sun. 1998. Solid State UV-LASER Technology for the Manufacture of High Performance Organic Modules. In IEEE/ECTC Proceedings, May 1998, 822–827.

    Google Scholar 

  45. Cable, A. 1997. Improvements in High Speed Microvia Formation Using Solid State Nd:YAG UV Lasers. In IPC EXPO, March 1997, S-2.

    Google Scholar 

  46. Tessier, T., and J. Aday. 1995. Casting Light on Recent Advancements in Laser Based MCM-L Processing. In Proceedings of International Conference on Multichip Modules, April 1995, 6–13.

    Google Scholar 

  47. Illyefalvi-Vitez, Z., and J. Pinkola. 1997. Application of Laser Engraving for the Fabrication of Fine Resolution Printed Wiring Laminates for MCM-Ls. In IEEE/ECTC Proceedings, May 1997, 502–510.

    Google Scholar 

  48. Enomoto, R., M. Asai, and N. Hirose. 1998. High Density MLB using Additive and Build-up Process. In Proceddings of the International Symposium on Microelectronics, November 1998, 399–404.

    Google Scholar 

  49. Kobayashi, K., N. Katagiri, and S. Koyama. 1999. Development of a Build Up Package with High Density of Circuits for High Pin Count Flip Chip Application. In IPC EXPO, March 1999, S01–4.

    Google Scholar 

  50. Burgess, L., and F. Pauri. 1999. Optimizing BGA to PCB Interconnections Using Multi-Depth Laser Drilled Blind Vias-in-Pad. Circuit World 25 (2): 31–34.

    Article  Google Scholar 

  51. Petefish, W., D. Noddin, and D. Hanson. 1998. High Density Organic Flip Chip Package Substrate Technology. In IEEE/ECTC Proceedings, May 1998, 1089–1097.

    Google Scholar 

  52. Li, L. 2004. Embedded Passives in Organic Substrate for RF Module and Assembly Characterization. In Proceedings of the 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, June 2004, 74–82.

    Google Scholar 

  53. Srinivasan, K., P. Muthana, R. Mandrekar, E. Engin, J. Choi, and M. Swaminathan. 2006. Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages. In Proceedings of the 7th International Symposium on Quality Electronic Design, March 2006, 286–291.

    Google Scholar 

  54. Pham, N., M. Cases, D. de Araujo, B. Mutnury, E. Matoglu, B. Herrman, and P. Patel. 2006. Embedded Capacitor in Power Distribution Design of High-End Server Packages. In IEEE/ECTC Proceedings, May 2006, 1677–1682.

    Google Scholar 

  55. Tanaka, H., T. Kariya, H. Nagata, K. Yoshikawa, K. Shimizu, H. Noauchi, and S. Kato. 2008. Embedded High-k Thin Film Capacitor in Organic Package. In IEEE/EPTC Proceedings, December 2008, 988–993.

    Google Scholar 

  56. Akahoshi, T., D. Mizutani, K. Fukui, S. Yamawaki, H. Fujisaki, M. Watanabe, and M. Koide. 2017. Development of CPU Package Embedded with Multilayer Thin Film Capacitor for Stabilization of Power Supply. In IEEE/ECTC Proceedings, May 2017, 179–184.

    Google Scholar 

  57. Lau, J.H., C. Chang, C. Chen, C. Ouyang, and R. Lee. 1999. Via-In-Pad (VIP) Substrates for Solder Bumped Flip Chip Applications. In Proceedings of the SMTA International Conference, September 1999, 128–136.

    Google Scholar 

  58. Lau, J.H., and C. Chang. 2000. An Overview of Microvia Technologies. Circuit World 26 (2): 22–32.

    Article  Google Scholar 

  59. Schmidt, W. 1999. High Performance Microvia PWB and MCM Applications. In IPC EXPO, S17-5-1–S17-5-8.

    Google Scholar 

  60. Shimizu, N., W. Kaneda, H. Arisaka, N. Koizumi, S. Sunohara, A. Rokugawa, and T. Koyama. 2013. Development of Organic Multi Chip Package for High Performance Application. In IMAPS International Symposium on Microelectronics, Orlando, FL, September 30–October 3, 2013, 414–419.

    Google Scholar 

  61. Oi, K., S. Otake, N. Shimizu, S. Watanabe, Y. Kunimoto, T. Kurihara, T. Koyama, M. Tanaka, L. Aryasomayajula, and Z. Kutlu. 2014. Development of New 2.5D Package With Novel Integrated Organic Interposer Substrate With Ultra-Fine Wiring and High Density Bumps. In IEEE 64th Electronic and Components Technology Conference, Orlando, FL, May 27–30, 2014, 348–353.

    Google Scholar 

  62. Koide, M., K. Fukuzono, H. Yoshimura, T. Sato, K. Abe, and H. Fujisaki. 2006. High-Performance Flip-Chip BGA Technology Based on Thin-Core and Coreless Package Substrate. In IEEE 56th Electronic and Components Technology Conference, San Diego, CA, May 30–June 2, 2006, 1869–1873.

    Google Scholar 

  63. Sung, R., K. Chiang, Y. Wang, and C. Hsiao. 2007. Comparative Analysis of Electrical Performance on Coreless and Standard Flip-Chip Substrate. In IEEE 57th Electronic and Components Technology Conference, Reno, NV, May 29–June 1, 2007, 1921–1924.

    Google Scholar 

  64. Lin, E., D. Chang, D. Jiang, Y. Wang, and C. Hsiao. 2007. Advantage and Challenge of Coreless Flip-Chip BGA. In International Microsystems, Packaging, Assembly and Circuits Technology, Taipei, Taiwan, October 1–3, 2007, 346–349.

    Google Scholar 

  65. Chang, D., Y. Wang, and C. Hsiao. 2007. High Performance Coreless Flip-Chip BGA Packaging Technology. In IEEE 57th Electronic and Components Technology Conference, Reno, NV, May 29–June 1, 2007, 1765–1768.

    Google Scholar 

  66. Savic, J., P. Aria, J. Priest, N. Dugbartey, R. Pomerleau, B. Shanker, M. Nagar, J. Lim, S. Teng, L. Li, and J. Xue. 2009. Electrical Performance Assessment of Advanced Substrate Technologies for High Speed Networking Applications. In IEEE 59th Electronic and Components Technology Conference, San Diego, CA, May 26–29, 2009, 1193–1199.

    Google Scholar 

  67. Kurashina, M., D. Mizutani, M. Koide, and N. Itoh. 2009. Precision Improvement Study of Thermal Warpage Prediction Technology for LSI Packages. In IEEE 59th Electronic and Components Technology Conference, San Diego, CA, May 26–29, 2009, 529–534.

    Google Scholar 

  68. Wang, J., Y. Ding, L. Liao, P. Yang, Y. Lai, and A. Tseng. Coreless Substrate for High Performance Flip Chip Packaging,” IEEE 11th International Conference on Electronic Packaging Technology.

    Google Scholar 

  69. Kimura, M. 2011. Shinko Officially Announces Volume Production of Coreless Substrate. Nikkei Electronics.

    Google Scholar 

  70. Fujimoto, D., K. Yamada, N. Ogawa, H. Murai, H. Fukai, Y. Kaneato, and M. Kato. 2011. New Fine Line Fabrication Technology on Glass-Cloth Prepreg Without Insulating Films for KG Substrate. In IEEE 61st Electronic and Components Technology Conference, Lake Buena Vista, FL, May 31–June 3, 2011, 387–391.

    Google Scholar 

  71. Kim, G., S. Lee, J. Yu, G. Jung, H. Yoo, and C. Lee. 2011. Advanced Coreless Flip-Chip BGA Package With High Dielectric Constant Thin Film Embedded Decoupling Capacitor. In IEEE 61st Electronic and Components Technology Conference, Lake Buena Vista, FL, May 31–June 3, 2011, 595–600.

    Google Scholar 

  72. Nickerson, R., R. Olmedo, R. Mortensen, C. Chee, S. Goyal, A. Low, and C. Gealer. 2012. Application of Coreless Substrate to Package on Package Architectures. In IEEE 62nd Electronic and Components Technology Conference, San Diego, CA, May 29–June 1, 2012, 1368–1371.

    Google Scholar 

  73. Kim, G., J. Yu, C. Park, S. Hong, J. Kim, G. Rinne, and C. Lee. 2012. Evaluation and Verification of Enhanced Electrical Performance of Advanced Coreless Flip-Chip BGA Package With Warpage Measurement Data. In IEEE 62nd Electronic and Components Technology Conference, San Diego, CA, May 29–June 1, 2012, 897–903.

    Google Scholar 

  74. Nishitani, Y. 2012. Coreless Packaging Technology for High-Performance Application. In IEEE/ECT/CMPT Seminar on Advanced Coreless Package Substrate and Material Technologies, Electronic Components and Technology Conference, San Diego, CA, May 29–June 1, 2012.

    Google Scholar 

  75. Kurashina, M., D. Mizutani, M. Koide, M. Watanabe, K. Fukuzono, and H. Suzuki. 2012. Low Warpage Coreless Substrate for Large-Size LSI Packages. In IEEE 62nd Electronic and Components Technology Conference, San Diego, CA, May 29–June 1, 2012, 1378–1383.

    Google Scholar 

  76. Kurashina, M., D. Mizutani, M. Koide, M. Watanabe, K. Fukuzono, N. Itoh, and H. Suzuki. 2012. Low Warpage Coreless Substrate for IC Packages. Transaction of the Japan Institute of Electronics Packaging 5 (1): 55–62.

    Article  Google Scholar 

  77. Manusharow, M., S. Muthukumar, E. Zheng, A. Sadiq, and C. Lee. 2012. Coreless Substrate Technology Investigation for Ultra-Thin CPU BGA Packaging. In IEEE 62nd Electronic and Components Technology Conference, San Diego, CA, May 29–June 1, 2012, 892–896.

    Google Scholar 

  78. Kim, J., S. Lee, J. Lee, S. Jung, and C. Ryu. 2012. Warpage Issues and Assembly Challenges Using Coreless Package Substrate. In IPC APEX Expo, San Diego, CA, February 28–March 1, 2012.

    Google Scholar 

  79. Sakuma, K., E. Blackshear, K. Tunga, C. Lian, S. Li, M. Interrante, O. Mantilla, and J. Nah. 2013. Flip Chip Assembly Method Employing Differential Heating/Cooling for Large Dies With Coreless Substrates. In IEEE 63rd Electronic and Components Technology Conference, Las Vegas, NV, May 28–31, 2013, 667–673.

    Google Scholar 

  80. Hahm, Y., M. Li, J. Yan, Y. Tretiakov, H. Lan, S. Chen, and S. Wong. 2016. Analysis and Measurement of Power Integrity and Jitter Impacts on Thin-Core and Coreless Packages. In IEEE 66th Electronic Components and Technology Conference, Las Vegas, NV, May 31–June 3, 2016, 387–392.

    Google Scholar 

  81. Baloglu, B., W. Lin, K. Stratton, M. Jimarez, and D. Brady. 2013. Warpage Characterization and Improvements for IC Packages With Coreless Substrate. In 46th International Symposium on Microelectronics, Orlando, FL, September 30–October 3, 2013, 260–284.

    Google Scholar 

  82. Sun, Y., X. He, Z. Yu, and L. Wan. 2013. Development of Ultra-Thin Low Warpage Coreless Substrate. In IEEE 63rd Electronic and Components Technology Conference, Las Vegas, NV, May 28–31, 2013, 1846–1849.

    Google Scholar 

  83. Lin, W., B. Baloglu, and K. Stratton. 2014. Coreless Substrate With Asymmetric Design to Improve Package Warpage. In IEEE 64th Electronic and Components Technology Conference, Orlando, FL, May 27–30, 2014, 1401–1406.

    Google Scholar 

  84. Liu, W., G. Xiaa, T. Liang, T. Li, X. Wang, J. Xie, S. Chen, and D. Yu. 2015. Development of High Yield, Reliable Fine Pitch Flip Chip Interconnects With Copper Pillar Bumps and Thin Coreless Substrate. In IEEE 65th Electronic and Components Technology Conference, San Diego, CA, May 26–29, 2015, 1713–1717.

    Google Scholar 

  85. Pendse, R., K. Kim, O. Kim, and K. Lee. 2006. Bond-On-Lead: A Novel Flip Chip Interconnection Technology for Fine Effective Pitch and High I/O Density. In IEEE 56th Electronic and Components Technology Conference, San Diego, CA, May 30–June 2, 2006, 16–23.

    Google Scholar 

  86. Pendse, R. 2008. Bump-On-Lead Flip Chip Interconnection. U.S. Patent No. 7,368,817, filed Nov. 10, 2004 and issued May 6, 2008.

    Google Scholar 

  87. Ouyang, E., M. Chae, S. Chow, R. Emigh, M. Joshi, R. Martin, and R. Pendse. 2010. Improvement of ELK Reliability in Flip Chip Packages Using Bond-On-Lead (BOL) Interconnect Structure. In IMAPS 43rd International Symposium on Microelectronics, Raleigh, NC, October 31–November 4, 2010, 197–203.

    Google Scholar 

  88. Pendse, R. 2011. Bump-On-Lead Flip Chip Interconnection. U.S. Patent No. 7,901,983, filed May 26, 2009 and issued March 8, 2011.

    Google Scholar 

  89. Pendse, R., C. Cho, M. Joshi, K. Kim, P. Kim, S. Kim, S. Kim, H. Lee, K. Lee, R. Martin, A. Murphy, V. Pandey, and C. Palar. 2010. Low CostmFlip Chip (LCFC): An Innovative Approach for Breakthrough Reduction in Flip Chip Package Cost. In IEEE 60th Electronic Components and Technology Conference, Las Vegas, NV, June 1–4, 2010.

    Google Scholar 

  90. Movva, S., S. Bezuk, O. Bchir, M. Shah, M. Joshi, R. Pendse, E. Ouyang, Y. Kim, S. Park, H. Lee, S. Kim, H. Bae, G. Na, and K. Lee. 2011. CuBOL (Cu-Column on BOL) Technology: A Low Cost Flip Chip Solution Scalable to High I/O Density, Fine Bump Pitch and Advanced Si-Nodes. In IEEE 61st Electronic and Components Technology Conference, Lake Buena Vista, FL, May 31–June 3, 2011, 601–607.

    Google Scholar 

  91. Lan, A., C. Hsiao, J.H. Lau, E. So, and B. Ma. 2012. Cu Pillar Exposed-Die Molded FCCSP for Mobile Devices. In IEEE 62nd Electronic and Components Technology Conference, San Diego, CA, May 29–June 1, 2012, 886–891.

    Google Scholar 

  92. Kuo, F., J. Lee, F. Chien, R. Lee, C. Mao, and J.H. Lau. 2014. Electromigration Performance of Cu Pillar Bump for Flip Chip Packaging With Bump on Trace by Using Thermal Compression Bonding. In IEEE 64th Electronic and Components Technology Conference, Orlando, FL, May 27–30, 2014, 56–61.

    Google Scholar 

  93. Li, M., D. Tian, Y. Cheung, L. Yang, and J.H. Lau. 2015. A High Throughput and Reliable Thermal Compression Bonding Process for Advanced Interconnections. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 603–608.

    Google Scholar 

  94. Liu, F., C. Nair, V. Sundaram, and R. Tummala. 2015. Advances in Embedded Traces for 1.5 lm RDL on 2.5D Glass Interposers. In IEEE 65th Electronic and Components Technology Conference, San Diego, CA, May 26–29, 2015, 1736–1741.

    Google Scholar 

  95. Chen, C., M. Lin, G. Liao, Y. Ding, and W. Cheng. 2015. Balanced Embedded Trace Substrate Design for Warpage Control. In IEEE 65th Electronic and Components Technology Conference, San Diego, CA, May 26–29, 2015, 193–199.

    Google Scholar 

  96. Zhang, L., and G. Joseph. 2015. Low Cost High Performance Bare Die PoP With Embedded Trace Coreless Technology and ‘Coreless Cored’ Build UpSubstrate Manufacture Process. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 882–887.

    Google Scholar 

  97. Lu, M. 2014. Challenges and Opportunities in Advanced IC Packaging. Chip Scale Review 18 (2): 5–8.

    Google Scholar 

  98. Lee, K., S. Cha, and P. Shim. 2016. Form Factor and Cost Driven Advanced Package Substrates for Mobile and IoT Applications. In China Semiconductor Technology International Conference, Shanghai, China, March 13–14, 2016.

    Google Scholar 

  99. Chen, K., S. Lee, P. Andry, C. Tsang, A. Topop, Y. Lin, Y.J. Lu, A. Young, M. Ieong, and W. Haensch. 2006. Structure, Design, and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits. In IEEE International Electron Devices Meeting, San Francisco, CA, December 11–13, 2006, 367–370.

    Google Scholar 

  100. Liu, F., R. Yu, A. Young, J. Doyle, X. Wang, L. Shi, K. Chen, X. Li, D. Dipaola, D. Brown, C. Ryan, J. Hagan, K. Wong, M. Lu, X. Gu, N. Klymko, E. Perfecto, A. Merryman, K. Kelly, S. Purushothaman, S. Koester, R. Wisnieff, and W. Haensch. 2008. A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding. In IEEE International Electron Devices Meeting, San Francisco, CA, December 15–17, 2008.

    Google Scholar 

  101. Yu, R., F. Liu, R. Polastre, K. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, T. Shaw, D. Dimilia, E. Kinser, A. Young, S. Purushothaman, S. Koester, and W. Haensch. 2009. Reliability of a 300-mm-Compatible 3DI Technology Based on Hybrid Cu-Adhesive Wafer Bonding. In Symposium on VLSI Technology, Honolulu, HI, June 16–18, 2009, 170–171.

    Google Scholar 

  102. Shigetou, A., T. Itoh, K. Sawada, and T. Suga. 2008. Bumpless Interconnect of 6-lm Pitch Cu Electrodes at Room Temperature. In Electronic Components and Technology Conference, Lake Buena Vista, FL, May 27–30, 2008, 1405–1409.

    Google Scholar 

  103. Tsukamoto, K., E. Higurashi, and T. Suga. 2010. Evaluation of Surface Microroughness for Surface Activated Bonding. In IEEE CPMT Symposium Japan, Tokyo, Japan, August 24–26, 2010, 1–4.

    Google Scholar 

  104. Kondou, R., C. Wang, and T. Suga. 2010. Room-Temperature Si-Si and Si-SiN Wafer Bonding. In IEEE CPMT Symposium Japan, Tokyo, Japan, August 24–26, 2010, 161–164.

    Google Scholar 

  105. Shigetou, A., T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, and T. Suga. 2006. Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method. IEEE Transactions on Advanced Packaging 29 (2): 218–226.

    Article  Google Scholar 

  106. Wang, C., and T. Suga. 2009. A Novel Moir_e Fringe Assisted Method for Nanoprecision Alignment in Wafer Bonding. In IEEE 59th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2009, 872–878.

    Google Scholar 

  107. Wang, C., and T. Suga. 2009. Moir_e Method for Nanoprecision Wafer-To-Wafer Alignment: Theory, Simulation, and Application. In IEEE International Conference on Electronic Packaging Technology and High-Density Packaging, Beijing, China, August 10–13, 2009, 219–224.

    Google Scholar 

  108. Higurashi, E., D. Chino, T. Suga, and R. Sawada. 2009. Au-Au Surface-Activated Bonding and Its Application to Optical Microsensors With 3-D Structure. IEEE Journal of Selected Topics in Quantum Electronics 15 (5): 1500–1505.

    Article  Google Scholar 

  109. Eitan, A., and K. Jing. 2015. Thermo-Compression Bonding for Fine-Pitch Copper-Pillar Flip Chip Interconnect—Tool Features as Enablers of Unique Technology. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 460–464.

    Google Scholar 

  110. Lau, J.H., and C. Chang. 2002. Characteristics and Reliability of Fast-Flow, Snap-Cure, and Reworkable Underfills for Solder Bumped Flip Chip on Low-Cost Substrates. IEEE Transactions on Electronics Packaging Manufacturing 25 (3): 231–230.

    Article  Google Scholar 

  111. Lau, J.H., and R. Lee. 2000. Fracture Mechanics Analysis of Low Cost Solder Bumped Flip Chip Assemblies With Imperfect Underfills. ASME Journal of Electronic Packaging 222 (4): 306–310.

    Article  Google Scholar 

  112. Lau, J.H., R. Lee, and C. Chang. 2000. Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board With Imperfect Underfill Encapsulants. IEEE Transactions on CPMT 23 (2): 323–333.

    Google Scholar 

  113. Lau, J.H., and S.W. Lee. 2000. Effects of Underfill Delamination and Chip Size on the Reliability of Solder Bumped Flip Chip on Board. IMAPS Transactions on International Journal of Microcircuits and Electronic Packaging 23 (1): 33–39.

    Google Scholar 

  114. Lau, J.H., C. Chang, and C. Chen. 1999. Characteristics and Reliability of No-Flow Underfills for Solder Bumped Flip Chip Assemblies. IMAPS Transactions on International Journal of Microcircuits and Electronic Packaging 22 (4): 370–381.

    Google Scholar 

  115. Lau, J.H., and C. Chang. 1999. How to Select Underfill Materials for Solder Bumped Flip Chips on Low Cost Substrates? IMAPS Transactions on International Journal of Microelectronics and Electronic Packaging 22 (1): 20–28.

    Google Scholar 

  116. Lau, J.H., and C. Chang. 1999. Characterization of Underfill Materials for Functional Solder Bumped Flip Chips on Board Applications. IEEE Transactions on CPMT, Part A 22 (1): 111–119.

    Google Scholar 

  117. Lau, J.H., C. Chang, and C. Ouyang. 1998. SMT Compatible No-Flow Underfill for Solder Bumped Flip Chip on Low-Cost Substrates. Journal of Electronics Manufacturing 8 (3–4): 151–164.

    Article  Google Scholar 

  118. Lau, J.H., C. Chang, and R. Chen. 1997. Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device. Journal of Electronics Manufacturing 7 (4): 269–277.

    Article  Google Scholar 

  119. Lau, J.H., and B. Wun. 1995. Characterization and Evaluation of the Underfill Encapsulants for Flip Chip Assembly. Soldering and Surface Mount Technology 21 (1): 25–27.

    Google Scholar 

  120. Lau, J.H., E. Schneider, and T. Baker. 1996. Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards. ASME Journal of Electronic Packaging 118 (2): 101–104.

    Article  Google Scholar 

  121. Lau, J.H. 1998. Flip Chip on PCBs With Anisotropic Conductive Film. Advanced Packaging, 44–48.

    Google Scholar 

  122. Lau, J.H., C. Chang, and R. Lee. 2000. Failure Analysis of Solder Bumped Flip Chip on Low-Cost Substrates. IEEE Transactions on Electronics Packaging Manufacturing 23 (1): 19–27.

    Article  Google Scholar 

  123. Lau, J.H., R. Lee, S. Pan, and C. Chang. 2002. Nonlinear Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications. ASME Journal of Electronics Packaging 124 (3): 205–211.

    Article  Google Scholar 

  124. Lau, J.H., Q. Zhang, M. Li, K. Yeung, Y. Cheung, N. Fan, Y. Wong, M. Zahn, and M. Koh. 2015. Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Assemblies. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 168–174.

    Google Scholar 

  125. Nakano, F., T. Soga, and S. Amagi. 1987. Resin-Insertion Effect on Thermal Cycle Resistivity of Flip-Chip Mounted LSI Devices. In International Symposium on Microelectronics, Minneapolis, MN, September 28–30, 1987, 536–541.

    Google Scholar 

  126. Lau, J.H., T. Krulevitch, W. Schar, M. Heydinger, S. Erasmus, and J. Gleason. 1993. Experimental and Analytical Studies of Encapsulated Flip Chip Solder Bumps on Surface Laminar Circuit Boards. Circuit World 19 (3): 18–24.

    Article  Google Scholar 

  127. Wun, B., and J.H. Lau. 1995. Characterization and Evaluation of the Underfill Encapsulants for Flip Chip Assembly. Circuit World 21 (3): 25–32.

    Article  Google Scholar 

  128. Lai, Y.M., C.K. Chee, E. Then, C.H. Ng, and M.F. Low. 2007. Capillary Underfill and Mold Encapsulation Method and Apparatus. U.S. Patent No. 7,262,077, filed September 30, 2003 and issued August 28, 2007.

    Google Scholar 

  129. Cremaldi, J., M. Gaynes, P. Brofman, N. Pesika, and E. Lewandowski. 2014. Time, Temperature, and Mechanical Fatigue Dependence on Underfill Adhesion. In IEEE 64th Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2014, 255–262.

    Google Scholar 

  130. Gilleo, K., B. Cotterman, and I.A. Chen. 2000. Molded Underfill for Flip Chip in Package. In Proceedings of High Density Interconnects, 2000, 28–31.

    Google Scholar 

  131. Rector, L.P., S. Gong, T.R. Miles, and K. Gaffney. 2000. Transfer Molding Encapsulation of Flip Chip Array Packages. International Journal of Microcircuits and Electronic Packaging 23 (4): 401–406.

    Google Scholar 

  132. Lee, J.Y., K.S. Oh, C.H. Hwang, C.H. Lee, and R.D.S. Amand. 2009. Molded Underfill Development for FlipStack CSP. In IEEE 59th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2009, 954–959.

    Google Scholar 

  133. Joshi, M., R. Pendse, V. Pandey, T.K. Lee, I.S. Yoon, J.S. Yun, Y.C. Kim, and H.R. Lee. 2010. Molded Underfill (MUF) Technology for Flip Chip Packages in Mobile Applications. In IEEE 60th Electronic Components and Technology Conference, Las Vegas, NV, June 1–4, 2010, 1250–1257.

    Google Scholar 

  134. Ferrandon, C., A. Jouve, S. Joblot, Y. Lamy, A. Schreiner, P. Montmeat, M. Pellat, M. Argoud, F. Fournel, G. Simon, and S. Cheramy. 2013. Innovative Wafer-Level Encapsulation and Underfill Material for Silicon Interposer Application. In IEEE 63rd Electronic Components and Technology Conference, Las Vegas, NV, May 28–31, 2013, 761–767.

    Google Scholar 

  135. Degani, Y., and L.A. Greenberg. 2002. Integrated circuit bonding method. European Patent 0 805 486 B1, February 6, 2002.

    Google Scholar 

  136. Lau, J.H., Q. Zhang, M. Li, K. Yeung, Y. Cheung, N. Fan, Y. Wong, M. Zahn, and M. Koh. 2015. Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates. IEEE Transactions on CPMT 5 (7): 1027–1035.

    Google Scholar 

  137. Wong, C.P., D. Baldwin, M.B. Vincent, B. Fennell, L.J. Wang, and S.H. Shi. 1998. Characterization of a No-Flow Underfill Encapsulant During the Solder Reflow Process. In IEEE 48th Electronic Components and Technology Conference, Seattle, WA, May 25–28, 1998, 1253–1259.

    Google Scholar 

  138. Lee, M., M. Yoo, J. Cho, S. Lee, J. Kim, C. Lee, D. Kang, C. Zwenger, and R. Lanzone. 2009. Study of Interconnection Process for Fine Pitch Flip Chip. In IEEE 48th Electronic Components and Technology Conference, Seattle, WA, May 25–28, 2009, 720–723.

    Google Scholar 

  139. Okayama, Y., M. Nakasato, K. Saitou, Y. Yanase, H. Kobayashi, T. Yamamoto, R. Usui, and Y. Inoue. 2010. Fine Pitch Connection and Thermal Stress Analysis of a Novel Wafer Level Packaging Technology Using Laminating Process. In IEEE 60th Electronic Components and Technology Conference, Las Vegas, NV, June 1–4, 2010, 287–292.

    Google Scholar 

  140. Honda, K., T. Enomoto, A. Nagai, and N. Takano. 2010. NCF for Wafer Lamination Process in Higher Density Electronic Packages. In IEEE 60th Electronic Components and Technology Conference, Las Vegas, NV, June 1–4, 2010, 1853–1860.

    Google Scholar 

  141. Honda, K., A. Nagai, M. Satou, S. Hagiwara, S. Tuchida, and H. Abe. 2012. NCF for Pre-Applied Process in Higher Density Electronic Package Including 3D-Package. In IEEE 62nd Electronic Components and Technology Conference, San Diego, CA, May 29–June 1, 2012, 385–392.

    Google Scholar 

  142. Fukushima, T., Y. Ohara, J. Bea, M. Murugesan, K.-W. Lee, T. Tanaka, and M. Koyanagi. 2012. Non-Conductive Film and Compression Molding Technology for Self-Assembly-Based 3D Integration. In IEEE 62nd Electronic Components and Technology Conference, San Diego, CA, May 29–June 1, 2012, 385–392.

    Google Scholar 

  143. Ito, Y., M. Murugesan, H. Kino, T. Fukushima, K. Lee, K. Choki, T. Tanaka, and M. Koyanagi. 2015. Development of Highly-Reliable Microbump Bonding Technology Using Self-Assembly of NCF-Covered KGDs and Multi-Layer 3D Stacking Challenges. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 336–341.

    Google Scholar 

  144. Choubey, A., E. Anzures, D. Fleming, A. Dhoble, L. Herong, R. Barr, J. Calvert, and J. Oh. 2014. Non-Conductive Film (NCF) Underfill for Flip Chip Assembly and High Reliability. In International Wafer Level Packaging Conference, San Jose, CA, November 11–13, 2014.

    Google Scholar 

  145. Lee, D., K. Kim, K. Kim, H. Kim, J. Kim, Y. Park, J. Kim, D. Kim, H. Park, J. Shin, J. Cho, K. Kwon, M. Kim, J. Lee, K. Park, B. Chung, and S. Hong. 2014. A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective Microbump I/O Test Methods Using 29 nm Process and TSV. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, February 9–13, 2014, 433–435.

    Google Scholar 

  146. Shin, J., Y. Kim, H. Lee, U. Kang, S. Seo, and K. Paik. 2015. Effects of Thermo-Compression Bonding Parameters on Joint Formation of Micro-Bumps in Non-Conductive Film (NCF). In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 910–915.

    Google Scholar 

  147. Lee, H., Y. Choi, J. Shin, and K. Paik. 2015. Wafer Level Packages (WLPs) Using B-Stage Non-Conductive Films (NCFs) for Highly Reliable 3D-TSV Micro-Bump Interconnection. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 331–335.

    Google Scholar 

  148. Hiner, D., D. Kim, S. Ahn, K. Kim, H. Kim, M. Lee, D. Kang, M. Kelly, R. Huemoeller, R. Radojcic, and S. Gu. 2015. Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film. In IEEE 65th Electronic Components and Technology Conference, San Diego, CA, May 26–29, 2015, 17–21.

    Google Scholar 

  149. Nonaka, T., Y. Kobayashi, N. Asahi, S. Niizeki, and K. Fujimaru. 2014. High Throughput Thermal Compression NCF Bonding. In IEEE 64th Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2014, 913–918.

    Google Scholar 

  150. Matsumura, K., M. Tomikawa, Y. Sakabe, and Y. Shiba. 2015. New Non Conductive Film for High Productivity Process. In IEEE CPMT Symposium Japan, Kyoto, Japan, November 9–11, 2015, 19–20.

    Google Scholar 

  151. Asahi, N., Y. Miyamoto, M. Nimura, Y. Mizutani, and Y. Arai. 2015. High Productivity Thermal Compression Bonding for 3D-IC. In IEEE International 3D Systems Integration Conference, Sendai, Japan, August 31–September 2, 2015, TS7.3.1–TS7.3.5.

    Google Scholar 

  152. Kagawa, Y., N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, N. Todaka, et al. 2016. Novel Stacked CMOS Image Sensor With Advanced Cu2Cu Hybrid Bonding. In IEEE/IEDM Proceedings, December 2016, 8.4.1–4.

    Google Scholar 

  153. Sukegawa, S., T. Umebayashi, T. Nakajima, H. Kawanobe, K. Koseki, I. Hirota, et al. 2013. A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor. In Proceedings of IEEE/ISSCC, San Francisco, CA, February 2013, 484–484.

    Google Scholar 

  154. Tseng, C., C. Liu, C. Wu, and D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, May 2016, 1–6.

    Google Scholar 

  155. Lau, J.H. 2016. Recent Advances and New Trends in Flip Chip Technology. ASME Transactions, Journal of Electronic Packaging 138(3):1–23.

    Google Scholar 

  156. Lau, J.H. 2017. Status and Outlooks of Flip Chip Technology. In IPC EXPO Proceedings, February 2017, 1–20.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ASM Pacific Technology, Hong Kong, New Territories, Hong Kong

    John H. Lau

Authors
  1. John H. Lau
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to John H. Lau .

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Lau, J.H. (2018). Flip Chip Technology Versus FOWLP. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_2

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-8884-1_2

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-8883-4

  • Online ISBN: 978-981-10-8884-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation