Skip to main content
SpringerLink
Log in

3D Integration

  • Chapter
  • First Online:
Fan-Out Wafer-Level Packaging

Abstract

The Electronics Industry has been the largest industry since 1996 and may well reach 2 trillion dollars by the end of 2018. 3D IC packaging, 3D IC integration, and 3D Si integration will be discussed in this chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 159.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Lau, J.H. 2013. Through-Silicon Vias for 3D Integration. New York: McGraw-Hill.

    Google Scholar 

  2. Lau, J.H. 2011. Reliability of RoHS Compliant 2D & 3D IC Interconnects. New York: McGraw-Hill.

    Google Scholar 

  3. Lau, J.H., C.K. Lee, C.S. Premachandran, and A. Yu. 2010. Advanced MEMS Packaging. New York: McGraw-Hill.

    Google Scholar 

  4. Moore, G. 1965. Cramming More Components Onto Integrated Circuits. Electronics 38 (8): 114–117.

    Google Scholar 

  5. Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, Y. Hsin, P. Chang, Y. Chang, J. Chen, S. Chen, C. Wu, H. Chang, C. Chien, C. Lin, T. Ku, R. Lo, and M. Kao. 2014. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. IMAPS Journal of Microelectronics and Electronic Packaging 11 (1): 16–24.

    Article  Google Scholar 

  6. Lau, J.H. 2014. The Future of Interposer for Semiconductor IC Packaging. Chip Scale Review 18 (1): 32–36.

    Google Scholar 

  7. Hsieh, M.C., S.T. Wu, C.J. Wu, and J.H. Lau. 2014. Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration. IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (1): 57–65.

    Article  Google Scholar 

  8. Lau, J.H. 2013. Supply Chains for High-Volume Manufacturing of 3D IC Integration. Chip Scale Review 17 (1): 33–39.

    Google Scholar 

  9. Khan, N., H. Li, S. Tan, S. Ho, V. Kripesh, D. Pinjala, J.H. Lau, and T. Chuan. 2013. 3-D Packaging with Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections. IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (2): 221–228.

    Article  Google Scholar 

  10. Lau, J.H., and G.Y. Tang. 2012. Effects of TSVs (Through-Silicon Vias) on Thermal Performances of 3D IC Integration System-In-Package (SiP). Journal of Microelectronics Reliability 52 (11): 2660–2669.

    Article  Google Scholar 

  11. Lau, J.H. 2012. Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry. ECS Transactions 44 (1): 805–825.

    Article  Google Scholar 

  12. Chien, H.C., J.H. Lau, Y. Chao, R. Tain, M. Dai, S.T. Wu, W. Lo, and M.J. Kao. 2012. Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV). IMAPS Journal of Microelectronics and Electronic Packaging 9 (2): 97–103.

    Article  Google Scholar 

  13. Chen, J.C., J.H. Lau, P.J. Tzeng, S. Chen, C. Wu, C. Chen, H. Yu, Y. Hsu, S. Shen, S. Liao, C. Ho, C. Lin, T.K. Ku, and M.J. Kao. 2012. Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration. IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (6): 956–963.

    Article  Google Scholar 

  14. Lee, C.K., T.C. Chang, J.H. Lau, Y. Huang, H. Fu, J. Huang, Z. Hsiao, C. Ko, R. Cheng, P. Chang, K. Kao, Y. Lu, R. Lo, and M. Kao. 2012. Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration. IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (8): 1229–1238.

    Article  Google Scholar 

  15. Sekhar, V.N., L. Shen, A. Kumar, T.C. Chai, X. Zhang, C.S. Premchandran, V. Kripesh, S. Yoon, and J.H. Lau. 2012. Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-K Stack. IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (1): 3–12.

    Google Scholar 

  16. Zhang, X., R. Rajoo, C.S. Selvanayagam, A. Kumar, V. Rao, N. Khan, V. Kripesh, J.H. Lau, D. Kwong, V. Sundaram, and R.R. Tummala. 2012. Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultra-thin Device. IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (16): 935–943.

    Article  Google Scholar 

  17. Wu, C., S. Chen, P. Tzeng, J.H. Lau, Y. Hsu, J. Chen, Y. Hsin, C. Chen, S. Shen, C. Lin, T. Ku, and M. Kao. 2012. Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration. IMAPS Journal of Microelectronics and Electronic Packaging 9 (1): 31–36.

    Article  Google Scholar 

  18. Lau, J.H., M.S. Zhang, and S.W.R. Lee. 2011. Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates. ASME Journal of Electronic Packaging 133 (3): 1–7.

    Article  Google Scholar 

  19. Chai, T.C., X. Zhang, J.H. Lau, C.S. Selvanayagam, D. Pinjala, Y. Hoe, Y. Ong, V. Rao, E. Wai, H. Li, E. Liao, N. Ranganathan, V. Kripesh, S. Liu, J. Sun, M. Ravi, C. Vath III, and Y. Tsutsumi. 2011. Development of Large Die Fine-Pitch Cu/Low-k FCBGA Package with Through Silicon Via (TSV) Interposer. IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (5): 660–672.

    Article  Google Scholar 

  20. Lau, J.H. 2011. TSV Interposers: The Most Cost-Effective Integrator for 3D IC Integration. Chip Scale Review 15 (5): 23–27.

    Google Scholar 

  21. Kumar, A., X. Zhang, Q. Zhang, M. Jong, G. Huang, V. Lee, V. Kripesh, C. Lee, J.H. Lau, D. Kwong, V. Sundaram, R.R. Tummula, and G. Meyer-Berg. 2011. Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor. IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (6): 841–851.

    Article  Google Scholar 

  22. Yu, A., J.H. Lau, S. Ho, A. Kumar, W. Hnin, W. Lee, M. Jong, V. Sekhar, V. Kripesh, D. Pinjala, S. Chen, C. Chan, C. Chao, C. Chiu, C. Huang, and C. Chen. 2011. Fabrication of High Aspect Ratio TSV and Assembly with Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology with High-Density Interconnects. IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (9): 1336–1344.

    Article  Google Scholar 

  23. Ong, Y.Y., S. Ho, V. Sekhar, X. Ong, J. Ong, X. Zhang, V. Kripesh, S. Yoon, J.H. Lau, Y. Lim, D. Yeo, K. Chan, Y. Zhang, J. Tan, and D. Sohn. 2011. Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-k Flip Chip Package. IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (3): 279–290.

    Article  Google Scholar 

  24. Lau, J.H. 2011. Overview and Outlook of TSV and 3D Integrations. Journal of Microelectronics International 28 (2): 8–22.

    Article  Google Scholar 

  25. Lau, J.H., C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, W. Li, S.-T. Wu, J.-F. Hung, R.-M. Tain, C.-H. Lin, Y.-C. Hsin, C.-C. Chen, S.-C. Chen, C.-Y. Wu, J.-C. Chen, C.-H. Chien, C.-W. Chiang, H. Chang, W.-L. Tsai, R.-S. Cheng, S.-Y. Huang, Y.-M. Lin, T.-C. Chang, C.-D. Ko, T.-H. Chen, S.-S. Sheu, S.-H. Wu, Y.-H. Chen, W.-C. Lo, T.-K. Ku, M.-J. Kao, and D.-Q. Hu. 2011. Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW). IMAPS Journal of Microelectronics and Electronic Packaging 8 (4): 171–178.

    Article  Google Scholar 

  26. Sheu, S., Z. Lin, J. Hung, J.H. Lau, P. Chen, S. Wu, K. Su, C. Lin, S. Lai, T. Ku, W. Lo, and M. Kao. 2011. An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration. IMAPS Journal of Microelectronics and Electronic Packaging 8 (4): 140–145.

    Article  Google Scholar 

  27. Lau, J.H. 2010. Critical Issues of 3D IC Integrations. IMAPS Journal of Microelectronics and Electronic Packaging 7 (1): 35–43.

    Article  Google Scholar 

  28. Lau, J.H., Y.S. Chan, and R.S.W. Lee. 2010. 3D IC Integration with TSV Interposers for High-Performance Applications. Chip Scale Review 14 (5): 26–29.

    Google Scholar 

  29. Lau, J.H. 2010. Design and Process of 3D MEMS Packaging. IMAPS Journal of Microelectronics and Electronic Packaging 7 (1): 10–15.

    Article  Google Scholar 

  30. Lau, J.H., R. Lee, M. Yuen, and P. Chan. 2010. 3D LED and IC Wafer Level Packaging. Journal of Microelectronics International 27 (2): 98–105.

    Article  Google Scholar 

  31. Lau, J.H. 2010. State-of-the-Art and Trends in 3D Integration. Chip Scale Review 14 (2): 22–28.

    Google Scholar 

  32. Tang, G.Y., S. Tan, N. Khan, D. Pinjala, J.H. Lau, A. Yu, V. Kripesh, and K. Toh. 2010. Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules. IEEE Transactions on Components, Packaging and Manufacturing Technology 33 (1): 184–195.

    Article  Google Scholar 

  33. Khan, N., V. Rao, S. Lim, H. We, V. Lee, X. Zhang, E. Liao, R. Nagarajan, T.C. Chai, V. Kripesh, and J.H. Lau. 2010. Development of 3-D Silicon Module with TSV for System in Packaging. IEEE Transactions on Components, Packaging and Manufacturing Technology 33 (1): 3–9.

    Article  Google Scholar 

  34. Lau, J.H., and G. Tang. 2009. Thermal Management of 3D IC Integration with TSV (Through Silicon Via). In IEEE 59th Electronic Components and Technology Conference, 635–640. San Diego, CA, 26–29 May 2009.

    Google Scholar 

  35. Yu, A., N. Khan, G. Archit, D. Pinjala, K. Toh, V. Kripesh, S. Yoon, and J.H. Lau. 2009. Fabrication of Silicon Carriers with TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages. IEEE Transactions on Components, Packaging and Manufacturing Technology 32 (3): 566–571.

    Article  Google Scholar 

  36. Selvanayagam, C., J.H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T.C. Chai. 2008. Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps. In IEEE 58th Electronic Components and Technology Conference, 1073–1081. Lake Buena Vista, FL, 27–30 May 2008.

    Google Scholar 

  37. Zhang, X., A. Kumar, Q.X. Zhang, Y.Y. Ong, S.W. Ho, C.H. Khong, V. Kripesh, J.H. Lau, D.-L. Kwong, V. Sundaram, R.R. Tummula, and G. Meyer-Berg. 2009. Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization. Journal of Sensors and Actuators A 156 (1): 2–7.

    Article  Google Scholar 

  38. Lau, J.H., C.-K. Lee, C.-J. Zhan, S.-T. Wu, Y.-L. Chao, M.-J. Dai, R.-M. Tain, H.-C. Chien, J.-F. Hung, C.-H. Chien, R.-S. Cheng, Y.-W. Huang, Y.-M. Cheng, L.-L. Liao, W.-C. Lo, and M.-J. Kao. 2014. Through-Silicon Hole Interposers for 3-D IC Integration. IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (9): 1407–1419.

    Article  Google Scholar 

  39. Lau, J.H., R.S.W. Lee, M. Yuen, J. Wu, C. Lo, H. Fan, and H. Chen. 2013. Apparatus Having Thermal-Enhanced and Cost-Effective 3D IC Integration Structure with Through Silicon Via Interposer. U.S. Patent No. 8,604,603.

    Google Scholar 

  40. Tummula, R., and M. Swaminathan. 2008. System-On-Package: Miniaturization of the Entire System. New York: McGraw-Hill.

    Google Scholar 

  41. Xie, J., H. Shi, Y. Li, Z. Li, A. Rahman, K. Chandrasekar, D. Ratakonda, M. Deo, K. Chanda, V. Hool, M. Lee, N. Vodrahalli, D. Ibbotson, and T. Verma. 2012. Enabling the 2.5D Integration. In Proceedings of IMAPS International Symposium on Microelectronics, 254–267. San Diego, CA, 9–13 Sept 2012.

    Google Scholar 

  42. Li, Z., H. Shi, J. Xie, and A. Rahman. 2012. Development of an Optimized Power Delivery System for 3D IC Integration with TSV Silicon Interposer. In IEEE 62nd Electronic Components and Technology Conference, 678–682. San Diego, CA, May 29–June 1 2012.

    Google Scholar 

  43. Kwon, W., M. Kim, J. Chang, S. Ramalingam, L. Madden, G. Tsai, S. Tseng, J. Lai, T. Lu, and S. Chin. 2013. Enabling a Manufacturable 3D Technologies and Ecosystem Using 28 nm FPGA with Stack Silicon Interconnect Technology. In IMAPS 46th International Symposium on Microelectronics, 217–222. Orlando, FL, Sept 30–Oct 3 2013.

    Google Scholar 

  44. Juergen, M., W.K. Zoschke, A. Klumpp, R. Wieland, M. Klein, L. Nebrich, A. Heinig, I. Limansyah, W. Weber, O. Ehrmann, and H. Reichl. 2009. 3D Integration of Image Sensor SiP Using TSV Silicon Interposer. In IEEE 11th Electronics Packaging Technology Conference, 795–800. Singapore, 9–11 Dec 2009.

    Google Scholar 

  45. Hsin, Y.C., C. Chen, J.H. Lau, P. Tzeng, S. Shen, Y. Hsu, S. Chen, C. Wn, J. Chen, T. Ku, and M. Kao. 2011. Effects of Etch Rate on Scallop of Through-Silicon Vias (TSVs) in 200 mm and 300 mm Wafers. In IEEE 61st Electronic Components and Technology Conference, 1130–1135. Orlando, FL, May 31–June 3 2011.

    Google Scholar 

  46. Garrou, P., C. Bower, and P. Ramm. 2009. 3D Integration: Technology and Applications. New York: Wiley.

    Google Scholar 

  47. Ramm, P., M. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel, and H. Reichl. 2008. Through Silicon Via Technology—Processes and Reliability for Wafer-Level 3D System Integration. In IEEE 58th Electronic Components and Technology Conference, 847–852. Orlando, FL, 27–30 May 2008.

    Google Scholar 

  48. Andry, P.S., C.K. Tsang, B.C. Webb, E.J. Sprogis, S.L. Wright, B. Bang, and D.G. Manzer. 2008. Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications. IBM Journal of Research and Development 52 (6): 571–581.

    Article  Google Scholar 

  49. Knickerbocker, J.U., P.S. Andry, B. Dang, R.R. Horton, C.S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, and S.L.Wright. 2008. 3-D Silicon Integration. In IEEE 58th Electronic Components and Technology Conference, 538–543. Lake Buena Vista, FL, 27–30 May 2008.

    Google Scholar 

  50. Shorey, A., S. Pollard, A. Streltsov, G. Piech, and R.Wagner. 2012. Development of Substrates for Through Glass Vias (TGV) for 3DS-IC Integration. In IEEE 62nd Electronic Components and Technology Conference, 289–291, San Diego, CA, May 29–June 1 2012.

    Google Scholar 

  51. Sundaram, V., Q. Chen, G. Kumar, F. Liu, R. Tummala, and Y. Suzuki. 2012. Low-Cost and Low-Loss 3D Silicon Interposer for High Bandwidth Logic-to-Memory Interconnections Without TSV in the Logic IC. In IEEE 62nd Electronic Components and Technology Conference, 292–297. San Diego, CA, May 29–June 1 2012.

    Google Scholar 

  52. Lee, H.S., Y.-S. Choi, E. Song, K. Choi, T. Cho, and S. Kang. 2007. Power Delivery Network Design for 3D SIP Integrated Over Silicon Interposer Platform. In IEEE 57th Electronic Components and Technology Conference, 1193–1198. Reno, NV, May 29–June 1 2007.

    Google Scholar 

  53. Messemaeker, J., O. Pedreira, B. Vandevelde, H. Philipsen, I. Wolf, E. Beyne, and K. Croes. 2013. Impact of Post-Plating Anneal and Through-Silicon Via Dimensions on Cu Pumping. In IEEE 63rd Electronic Components and Technology Conference, 586–591. Las Vegas, NV, 28–31 May 2013.

    Google Scholar 

  54. Morikawa, Y., T. Murayama, Y. Nakamuta, T. Sakuishi, A. Suzuki, and K. Suu. 2013. Total Cost Effective Scallop Free Si Etching for 2.5D & 3D TSV Fabrication Technologies in 300 mm Wafer. In IEEE 63rd Electronic Components and Technology Conference, 605–607. Las Vegas, NV, 28–31 May 2013.

    Google Scholar 

  55. Shi, X., P. Sun, Y. Tsui, P. Law, S. Yau, C. Leung, Y. Liu, C. Chung, S. Ma, M. Miao, and Y. Jin. 2010. Development of CMOS-Process-Compatible Interconnect Technology for 3D-Stacking of NAND Flash Memory Chips. In IEEE 60th Electronic Components and Technology Conference, 74–78. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  56. Kikuchi, K., C. Ueda, K. Takemura, O. Shimada, T. Gomyo, Y. Takeuchi, T. Ookubo, K. Baba, M. Aoyagi, T. Sudo, and K. Otsuka. 2010. Low-Impedance Evaluation of Power Distribution Network for Decoupling Capacitor Embedded Interposers of 3-D Integrated LSI System. In IEEE 60th Electronic Components and Technology Conference, 1455–1460. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  57. Sridharan, V., S. Min, V. Sundaram, V. Sukumaran, S. Hwang, H. Chan, F. Liu, C. Nopper, and R. Tummala. 2010. Design and Fabrication of Bandpass Filters in Glass Interposer with Through-Package-Vias (TPV). In IEEE 60th Electronic Components and Technology Conference, 530–535. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  58. Lau, J.H. 2016. Recent Advances and New Trends in Flip Chip Technology. ASME Transactions, Journal of Electronic Packaging 138 (3): 1–23.

    Google Scholar 

  59. Sakuma, K., K. Sueoka, S. Kohara, K. Matsumoto, H. Noma, T. Aoki, Y. Oyama, H. Nishiwaki, P.S. Andry, C.K. Tsang, J. Knickerbocker, and Y. Orii. 2010. IMC Bonding for 3D Interconnection. In IEEE 60th Electronic Components and Technology Conference, 864–871. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  60. Doany, F., B. Lee, C. Schow, C. Tsang, C. Baks, Y. Kwark, R. John, J. Knickerbocker, and J. Kash. 2010. Terabit/s-Class 24-Channel Bidirectional Optical Transceiver Module Based on TSV Si Carrier for Board-Level Interconnects. In IEEE 60th Electronic Components and Technology Conference, 58–65. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  61. Khan, N., D. Wee, O. Chiew, C. Sharmani, L. Lim, H. Li, and S. Vasarala. 2010. Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process. In IEEE 60th Electronic Components and Technology Conference, 884–888. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  62. Trigg, A., L. Yu, X. Zhang, C. Chong, C. Kuo, N. Khan, and D. Yu. 2010. Design and Fabrication of a Reliability Test Chip for 3D-TSV. In IEEE 60th Electronic Components and Technology Conference, 79–83. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  63. Agarwal, R., W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan. 2010. Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking. In IEEE 60th Electronic Components and Technology Conference, 858–863. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  64. Lau, J.H. 2014. Overview and Outlook of 3D IC Packaging, 3D IC Integration, and 3D Si Integration. ASME Transactions, Journal of Electronic Packaging 136 (4): 1–15.

    Google Scholar 

  65. Liu, H., K. Wang, K. Aasmundtveit, and N. Hoivik. (2010). Intermetallic Cu3Sn as Oxidation Barrier for Fluxless Cu-Sn Bonding. In IEEE 60th Electronic Components and Technology Conference, 853–857. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  66. Kang, I., G. Jung, B. Jeon, J. Yoo, and S. Jeong. 2010. Wafer Level Embedded System in Package (WL-eSiP) for Mobile Applications. In IEEE 60th Electronic Components and Technology Conference, 309–315. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  67. Dorsey, P. 2010. Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency. San Jose, CA: Xilinx Inc. White Paper Virtex-7 FPGAs, WP380 (v1).

    Google Scholar 

  68. Lau, J.H., C. Lee, C. Zhan, S. Wu, Y. Chao, M. Dai, R. Tain, H. Chien, C. Chien, R. Cheng, Y. Huang, Y. Lee, Z. Hsiao, W. Tsai, P. Chang, H. Fu, Y. Cheng, L. Liao, W. Lo, and M. Kao. 2014. Low-Cost TSH (Through-Silicon Hole) Interposers for 3D IC Integration. In IEEE 64th Electronic Components and Technology Conference, 290–296. Orlando, FL, 27–30 May 2014.

    Google Scholar 

  69. Akasaka, Y. 1986. Three-Dimensional IC Trends. Proceedings of the IEEE 74 (12): 1703–1714.

    Article  Google Scholar 

  70. Akasaka, Y., and T. Nishimura. 1986. Concept and Basic Technologies for 3-D IC Structure. In IEEE International Electron Devices Meetings, 488–491. Los Angeles, CA, 7–10 Dec 1986.

    Google Scholar 

  71. Dang, B., P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, and J. Knickerbocker. 2010. CMOS Compatible Thin Wafer Processing Using Temporary Mechanical Wafer, Adhesive and Laser Release of Thin Chips/Wafers for 3D Integration. In IEEE 60th Electronic Components and Technology Conference, 1393–1398. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  72. Bieck, F., S. Spiller, F. Molina, M. Töpper, C. Lopper, I. Kuna, T. Seng, and T. Tabuchi. 2010. Carrierless Design for Handling and Processing of Ultrathin Wafers. In IEEE 60th Electronic Components and Technology Conference, 316–322. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  73. Itabashi, T., and M. Zussman. 2010. High Temperature Resistant Bonding Solutions Enabling Thin Wafer Processing (Characterization of Polyimide Base Temporary Bonding Adhesive for Thinned Wafer Handling). In IEEE 60th Electronic Components and Technology Conference, 1877–1880. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  74. Zoschke, K., M. Wegner, M. Wilke, N. Jürgensen, C. Lopper, I. Kuna, V. Glaw, J. Röder, O. Wünsch, M.J. Wolf, O. Ehrmann, and H. Reichl. 2010. Evaluation of Thin Wafer Processing Using a Temporary Wafer Handling System as Key Technology for 3D System Integration. In IEEE 60th Electronic Components and Technology Conference, 1385–1392. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  75. Charbonnier, J., R. Hida, D. Henry, S. Cheramy, P. Chausse, M. Neyret, O. Hajji, G. Garnier, C. Brunet-Manquat, P. Haumesser, L. Vandroux, R. Anciant, N. Sillon, A. Farcy, M. Rousseau, J. Cuzzocrea, G. Druais, and E. Saugier. 2010. Development and Characterisation of a 3D Technology Including TSV and Cu Pillars for High Frequency Applications. In IEEE 60th Electronic Components and Technology Conference, 1077–1082. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  76. Sun, Y., X. Li, J. Gandhi, S. Luo, and T. Jiang. (2010). Adhesion Improvement for Polymer Dielectric to Electrolytic-Plated Copper. In IEEE 60th Electronic Components and Technology Conference, 1106–1111. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  77. Kawano, M., N. Takahashi, M. Komuro, and S. Matsui. 2010. Low-Cost TSV Process Using Electroless Ni Plating for 3D Stacked DRAM. In IEEE 60th Electronic Components and Technology Conference, 1094–1099. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  78. Malta, D., C. Gregory, D. Temple, T. Knutson, C. Wang, T. Richardson, Y. Zhang, and R. Rhoades. 2010. Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects. In IEEE 60th Electronic Components and Technology Conference, 1769–1775. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  79. Campbell, D.V. 2010. Yield Modeling of 3D Integrated Wafer Scale Assemblies. In IEEE Proceedings of ECTC, 60th Electronic Components and Technology Conference, 1935–1938. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  80. Archard, D., K. Giles, A. Price, S. Burgess, and K. Buchanan. 2010. Low Temperature PECVD of Dielectric Films for TSV Applications. In IEEE 60th Electronic Components and Technology Conference, 764–768. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  81. Shigetou, A., and T. Suga. 2010. Modified Diffusion Bonding for Both Cu and SiO2 at 150 °C in Ambient Air. In IEEE 60th Electronic Components and Technology Conference, 872–877. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  82. Amagai, M., and Y. Suzuki. 2010. TSV Stress Testing and Modeling. In IEEE 60th Electronic Components and Technology Conference, 1273–1280. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  83. Lu, K., S. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. Ho. 2010. Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects. In IEEE 60th Electronic Components and Technology Conference, 40–45. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  84. Miyazaki, C., H. Shimamoto, T. Uematsu, Y. Abe, K. Kitaichi, T. Morifuji, and S. Yasunaga. 2010. Development of High Accuracy Wafer Thinning and Pickup Technology for Thin Wafer (Die). In IEEE CPMT Symposium, 139–142. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  85. Cho, J., K. Yoon, J. Pak, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim. 2010. Guard Ring Effect for Through Silicon Via (TSV) Noise Coupling Reduction. In IEEE CPMT Symposium, 151–154. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  86. Nonake, T., K. Fujimaru, A. Shimada, N. Asahi, Y. Tatsuta, H. Niwa, and Y. Tachibana. 2010. Wafer and/or Chip Bonding Adhesives for 3D Package. In IEEE CPMT Symposium, 169–172. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  87. Gupta, A., S. Kannan, B. Kim, F. Mohammed, and B. Ahn. 2010. Development of Novel Carbon Nanotube TSV Technology. In IEEE 60th Electronic Components and Technology Conference, 1699–1702. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  88. Kannan, S., A. Gupta, B. Kim, F. Mohammed, and B. Ahn. 2010. Analysis of Carbon Nanotube Based Through Silicon Vias. 2010. In IEEE 60th Electronic Components and Technology Conference, 51–57. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  89. Lau, J.H. 2010. TSV Manufacturing Yield and Hidden Costs for 3D IC Integration. In IEEE 60th Electronic Components and Technology Conference, 1031–1041. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  90. Chen, K., S. Lee, P. Andry, C. Tsang, A. Topop, Y. Lin, Y.J. Lu, A. Young, M. Ieong, and W. Haensch. 2006. Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits. In IEEE International Electron Devices Meeting, 367–370. San Francisco, CA, 11–13 Dec 2006.

    Google Scholar 

  91. Liu, F., R. Yu, A. Young, J. Doyle, X. Wang, L. Shi, K. Chen, X. Li, D. Dipaola, D. Brown, C. Ryan, J. Hagan, K. Wong, M. Lu, X. Gu, N. Klymko, E. Perfecto, A. Merryman, K. Kelly, S. Purushothaman, S. Koester, R. Wisnieff, and W. Haensch. 2008. A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding. In IEEE International Electron Devices Meeting, San Francisco, CA, 15–17 Dec 2008.

    Google Scholar 

  92. Yu, R., F. Liu, R. Polastre, K. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, T. Shaw, D. Dimilia, E. Kinser, A. Young, S. Purushothaman, S. Koester, and W. Haensch. 2009. Reliability of a 300-mm-Compatible 3DI Technology Based on Hybrid Cu-Adhesive Wafer Bonding. In Symposium on VLSI Technology, 170–171. Honolulu, HI, 16–18 June 2009.

    Google Scholar 

  93. Shigetou, A., T. Itoh, K. Sawada, and T. Suga. 2008. Bumpless Interconnect of 6-lm Pitch Cu Electrodes at Room Temperature. In IEEE 58th Electronic Components and Technology Conference, 1405–1409. Lake Buena Vista, FL, 27–30 May 2008.

    Google Scholar 

  94. Tsukamoto, K., E. Higurashi, and T. Suga. 2010. Evaluation of Surface Microroughness for Surface Activated Bonding. In Proceedings of IEEE CPMT Symposium Japan, 147–150. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  95. Kondou, R., C. Wang, and T. Suga. 2010. Room-Temperature Si-Si and Si-SiN Wafer Bonding. In IEEE CPMT Symposium, 161–164. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  96. Shigetou, A., T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, and T. Suga. 2006. Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method. IEEE Transactions on Advanced Packaging 29 (2): 218–226.

    Article  Google Scholar 

  97. Wang, C., and T. Suga. 2009. A Novel Moire Fringe Assisted Method for Nanoprecision Alignment in Wafer Bonding. In IEEE 59th Electronic Components and Technology Conference, 872–878. San Diego, CA, 25–29 May 2009.

    Google Scholar 

  98. Wang, C., and T. Suga. 2009. Moire Method for Nanoprecision Wafer-to-Wafer Alignment: Theory, Simulation and Application. In IEEE International Conference on Electronic Packaging Technology and High-Density Packaging, 219–224. Beijing, China, 10–13 Aug 2009.

    Google Scholar 

  99. Higurashi, E., D. Chino, T. Suga, and R. Sawada. 2009. Au-Au Surface-Activated Bonding and Its Application to Optical Microsensors with 3-D Structure. IEEE Journal of Selected Topics in Quantum Electronics 15 (5): 1500–1505.

    Article  Google Scholar 

  100. Burns, J., B. Aull, C. Keast, C. Chen, C. Chen, C. Keast, J. Knecht, V. Suntharalingam, K. Warner, P. Wyatt, and D. Yost. 2006. A Wafer-Scale 3-D Circuit Integration Technology. IEEE Transactions on Electron Devices 53 (10): 2507–2516.

    Article  Google Scholar 

  101. Chen, C., K. Warner, D. Yost, J. Knecht, V. Suntharalingam, C. Chen, J. Burns, and C. Keast. 2007. Scaling Three-Dimensional SOI Integrated-Circuit Technology. In IEEE International SOI Conference, 87–88. Indian Wells, CA, 1–4 Oct 2007.

    Google Scholar 

  102. Chen, C., C. Chen, D. Yost, J. Knecht, P. Wyatt, J. Burns, K. Warner, P. Gouker, P. Healey, B. Wheeler, and C. Keast. 2008. Three-Dimensional Integration of Silicon-on-Insulator RF Amplifier. Electronics Letters 44 (12): 746–747.

    Article  Google Scholar 

  103. Chen, C., C. Chen, D. Yost, J. Knecht, P. Wyatt, J. Burns, K. Warner, P. Gouker, P. Healey, B. Wheeler, and C. Keast. 2009. Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers. In IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, CA, 19–21 Jan 2009.

    Google Scholar 

  104. Chen, C., C. Chen, P. Wyatt, P. Gouker, J. Burns, J. Knecht, D. Yost, P. Healey, and C. Keast. 2008. Effects of Through-BOX Vias on SOI MOSFETs. In IEEE International Symposium on VLSI Technology, Systems and Applications, 95–96. Hsinchu, Taiwan, 21–23 Apr 2008.

    Google Scholar 

  105. Chen, C., C. Chen, J. Burns, D. Yost, K. Warner, J. Knecht, D. Shibles, and C. Keast. 2007. Thermal Effects of Three-Dimensional Integrated Circuit Stacks. In IEEE International SOI Conference, 91–92. Indian Wells, CA, 1–4 Oct 2007.

    Google Scholar 

  106. Aull, B., J. Burns, C. Chen, B. Felton, H. Hanson, C. Keast, J. Knecht, A. Loomis, M. Renzi, A. Soares, V. Suntharalingam, K. Warner, D. Wolfson, D. Yost, and D. Young. 2006. Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers. IEEE International Solid-State Circuits Conference, 1179–1188. San Francisco, CA, 6–9 Feb 2006.

    Google Scholar 

  107. Chatterjee, R., M. Fayolle, P. Leduc, S. Pozder, B. Jones, E. Acosta, B. Charlet, T. Enot, M. Heitzmann, M. Zussy, A. Roman, O. Louveau, S. Maitreqean, D. Louis, N. Kernevez, N. Sillon, G. Passemard, V. Pol, V. Mathew, S. Garcia, T. Sparks, and Z. Huang. 2007. Three-Dimensional Chip Stacking Using a Wafer-to-Wafer Integration. In IEEE International Interconnect Technology Conference, 81–83. Burlingame, CA, 4–6 June 2007.

    Google Scholar 

  108. Ledus, P., F. Crecy, M. Fayolle, M. Fayolle, B. Charlet, T. Enot, M. Zussy, B. Jones, J. Barbe, N. Kernevez, N. Sillon, S. Maitreqean, D. Louis, and G. Passemard. 2007. Challenges for 3D IC Integration: Bonding Quality and Thermal Management. In IEEE International Interconnect Technology Conference, 210–212. Burlingame, CA, 4–6 June 2007.

    Google Scholar 

  109. Poupon, G., N. Sillon, D. Henry, C. Gillot, A. Mathewson, L. Cioccio, B. Charlet, P. Leduc, M. Vinet, and P. Batude. 2009. System on Wafer: A New Silicon Concept in Sip. Proceedings of the IEEE 97 (1): 60–69.

    Article  Google Scholar 

  110. Fujimoto, K., N. Maeda, H. Kitada, Y. Kim, A. Kawai, K. Arai, T. Nakamura, K. Suzuki, and T. Ohba. 2010. Development of Multi-Stack Process on Wafer-on-Wafer (WoW). In IEEE CPMT Symposium, 157–160. Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  111. Lee, C., A. Yu, L. Yan, H. Wang, J. Han, Q. Zhang, and J.H. Lau. 2009. Characterization of Intermediate In/Ag Layers of Low Temperature Fluxless Solder Based Wafer Bonding for MEMS Packaging. Journal of Sensors and Actuators A 154 (1): 85–91.

    Article  Google Scholar 

  112. Yu, D.Q., C. Lee, L. Yan, M. Thew, and J.H. Lau. 2009. Characterization and Reliability Study of Low Temperature Hermetic Wafer Level Bonding Using In/Sn Interlayer and Cu/Ni/Au Metallization. Journal of Alloys and Compounds 485 (1–2): 444–450.

    Article  Google Scholar 

  113. Yu, D.Q., C. Lee, L.L. Yan, W.K. Choi, A. Yu, and J.H. Lau. 2009. The Role of Ni Buffer Layer on High Yield Low Temperature Hermetic Wafer Bonding Using In/Sn/Cu Metallization. Applied Physics Letters 94 (3): 034105.

    Article  Google Scholar 

  114. Reed, J., M. Lueck, C. Gregory, A. Huffman, J. Lannon Jr., and D. Temple. 2010. High-Density Interconnect at 10 lm Pitch with Mechanically Keyed Cu/Sn-Cu and Cu-Cu Bonding for 3-D Integration. In IEEE 60th Electronic Components and Technology Conference, 846–852. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  115. Okoro, C., R. Agarwal, P. Limaye, B. Vandevelde, D. Vandepitte, and E. Beyne. 2010. Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration. In IEEE 60th Electronic Components and Technology Conference, 1370–1375. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  116. Huyghebaert, C., J. Olmen, O. Chukwudi, J. Coenen, A. Jourdain, M. Cauwenberghe, R. Agarwahl, R.A. Phommahaxay, M. Stucchi, and P. Soussan, Enabling 10 lm Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias. In IEEE 60th Electronic Components and Technology Conference, 1083–1087. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  117. Di Cioccio, L., P. Gueguen, E. Grouiller, L. Vandroux, V. Delaye, M. Rivoire, J. Lugand, and L. Clavelier. 2010. Vertical Metal Interconnect Thanks to Tungsten Direct Bonding. In IEEE 60th Electronic Components and Technology Conference, 1359–1363. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  118. Gueguen, P., L. Di Cioccio, P. Morfouli, M. Zussy, J.Dechamp, L. Bally, and L. Clavelier. 2010. Copper Direct Bonding: An Innovative 3D Interconnect. In IEEE 60th Electronic Components and Technology Conference, 878–883. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  119. Taibi, R., L. Di Cioccio, C. Chappaz, L. Chapelon, P. Gueguen, J. Dechamp, R. Fortunier, and L. Clavelier. 2010. Full Characterization of Cu/Cu Direct Bonding for 3D Integration. In IEEE 60th Electronic Components and Technology Conference, 219–225. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  120. Lim, D., J. Wei, C. Ng, and C. Tan. 2010. Low Temperature Bump-less Cu-Cu Bonding Enhancement with Self Assembled Monolayer (SAM) Passivation for 3-D Integration. In IEEE 60th Electronic Components and Technology Conference, 1364–1369. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  121. Yu, D.Q., Y. Li, C. Lee, W. Choi, S. Thew, C. Foo, and J.H. Lau. 2009. Wafer-Level Hermetic Bonding Using Sn/In and Cu/Ti/Au Metallization. IEEE Transactions on Components, Packaging and Manufacturing Technology 32 (4): 926–934.

    Article  Google Scholar 

  122. Campbell, D. 2010. Process Characterization Vehicles for 3D Integration. In IEEE 60th Electronic Components and Technology Conference, 1112–1116. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  123. Made, R., C. Gan, L. Yan, A. Yu, S. Yoon, J.H. Lau, and C. Lee. 2009. Study of Low Temperature Thermocompression Bonding in Ag-In Solder for Packaging Applications. Journal of Electronic Materials 38 (2): 365–371.

    Article  Google Scholar 

  124. Pang, X., T.T. Chua, H.Y. Li, E.B. Liao, W.S. Lee, and F.X. Che. 2010. Characterization and Management of Wafer Stress for Various Pattern Densities in 3D Integration Technology. In IEEE 60th Electronic Components and Technology Conference, 1866–1869. Las Vegas, NV, 1–4 June 2010.

    Google Scholar 

  125. Yan, L.L., C.K. Lee, D.Q. Yu, A. Yu, W. Choi, J.H. Lau, and S. Yoon. 2009. A Hermetic Seal Using Composite Thin Solder In/Sn as Intermediate Layer and Its Interdiffusion Reaction with Cu. Journal of Electronic Materials 38 (2): 200–207.

    Article  Google Scholar 

  126. Lau, J.H. 2010. Who Invented the TSV (TSV) and When? Posted at 3D InCites on 24 Apr 2010. http://www.semineedle.com/posting/31171.

  127. Lau, J.H. 2010. Heart and Soul of 3D IC Integration. Posted at 3D InCites on 29 June 2010. http://www.semineedle.com/posting/34277.

  128. Harman, G. 2010. Wire Bonding in Microelectronics. New York: McGraw-Hill.

    Google Scholar 

  129. Lau, J.H. 1996. Flip Chip Technology. New York: McGraw-Hill.

    Google Scholar 

  130. Lau, J.H. 2000. Low Cost Flip Chip Technologies. New York: McGraw-Hill.

    Google Scholar 

  131. Pang, W., R. Ruby, R. Parker, P.W. Fisher, M.A. Unkrich, and J.D. Larson III. 2008. A Temperature-Stable Film Bulk Acoustic Wave Oscillator. IEEE Electron Device Letters 29 (4): 315–318.

    Article  Google Scholar 

  132. Small, M., R. Ruby, S. Ortiz, R. Parker, F. Zhang, J. Shi, and B. Otis. 2011. Wafer-Scale Packaging for FBAR-Based Oscillators. In Joint Conference of the IEEE International Frequency Control and the European Frequency and Time Forum, San Francisco, CA, 2–5 May 2011.

    Google Scholar 

  133. Wakabayashi, H., H.K. Yamaguchi, M. Okano, S. Kuramochi, O. Kumagai, S. Sakane, M. Ito, M. Hatano, M. Kikuchi, Y. Yamagata, T. Shikanai, K. Koseki, K. Mabuchi, Y. Maruyama, K. Akiyama, E. Miyata, T. Honda, and M. Ohashi. 2010. A 1/2.3-Inch 10.3 M Pixel 50 Frame/s Back-Illuminated CMOS Image Sensor. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, 411–412. San Francisco, CA, 7–11 Feb 2010.

    Google Scholar 

  134. Sukegawa, S., T. Umebayashi, T. Nakajima, H. Kawanobe, K. Koseki, I. Hirota, T. Haruta, M. Kasai, K. Fukumoto, T. Wakano, K. Inoue, H. Takahashi, T. Nagano, Y. Nitta, T. Hirayama, and N. Fukushima. 2013. A 1/4-Inch 8 M Pixel Back-Illuminated Stacked CMOS Image Sensor. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, 484. San Francisco, CA, 17–21 Feb 2013.

    Google Scholar 

  135. Gat, A., L. Gerzberg, J. Gibbons, T. Mages, J. Peng, and J. Hong. 1978. CW Laser of Polyerystalline Silicon: Crystalline Structure and Electrical Properties. Applied Physics Letters 33 (8): 775–778.

    Article  Google Scholar 

  136. Tuckerman, D.B., L.O. Bauer, N.E. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.M. Lin, K. Lin, S. Nguyen, and V. Thipphavong. 1994. Laminated Memory: A New Three-Dimensional Packaging Technology for MCMs. In IEEE Multi-Chip Module Conference, 58–63. Santa Cruz, CA, 15–17 Mar 1994.

    Google Scholar 

  137. Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In IEEE 62nd Electronic Components and Technology Conference, 1250–1254. San Diego, CA, May 29–June 1 2012.

    Google Scholar 

  138. Lim, S., V. Rao, W. Hnin, W. Ching, V. Kripesh, C. Lee, J.H. Lau, J. Milla, and A. Fenner. 2008. Process Development and Reliability of Microbumps. In IEEE Electronic Packaging Technology Conference, 367–372. Singapore, 9–12 Dec 2008.

    Google Scholar 

  139. Kagawa, Y., N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, and N. Todaka, Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding. In IEEE/IEDM Proceedings, Dec 2016, 8.4.1-4.

    Google Scholar 

  140. Sukegawa, S., T. Umebayashi, T. Nakajima, H. Kawanobe, K. Koseki, and I. Hirota. 2013. A 1/4-inch 8 Mpixel Back-Illuminated Stacked CMOS Image Sensor. In Proceedings of IEEE/ISSCC, 484. San Francisco, CA, Feb 2013.

    Google Scholar 

  141. JEDEC. 2011. Standard No. JESD229, Wide I/O Single Data Rate (Wide I/O SDR) and Standard No. JESD229-2, Wide I/O 2 (Wide I/O2). In JEDEC, Arlington, VA.

    Google Scholar 

  142. JEDEC. 2013. Standard No. JESD235, High Bandwidth Memory (HBM) DRAM. In JEDEC, Arlington, VA.

    Google Scholar 

  143. Graham, S. 2013. Development of Hybrid Memory Cube. 3D IC Panel Discussion. In IMAPS 46th International Symposium on Microelectronics, Orlando, FL, Sept 30–Oct 3 2013.

    Google Scholar 

  144. Brunnbauer, M., E. Feurgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In IEEE 56th Electronic Components and Technology Conference, 547–551. San Diego, CA, May 30–June 2 2006.

    Google Scholar 

  145. Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In IEEE 8th Electronics Packaging Technology Conference, Singapore, 6–8 Dec 2006.

    Google Scholar 

  146. Meyer, T., G. Ofner, S. Bradl, M. Brunnbauer, and R. Hagen. 2008. Embedded Wafer Level Ball Grid Array (eWLB). In IEEE 10th Electronics Packaging Technology Conference, 994–998. Singapore, 9–12 Dec 2008.

    Google Scholar 

  147. Brunnbauer, M., T. Meyer, G. Ofner, K. Mueller, and R. Hagen. 2008. Embedded Wafer Level Ball Grid Array (eWLB). In 33rd IEEE/CPMT International Electronic Manufacturing Technology Symposium, Penang, Malaysia, 4–6 Nov 2008.

    Google Scholar 

  148. Pressel, K., G. Beer, T. Meyer, M. Wojnowski, M. Fink, G. Ofner, and B. Römer. 2010. Embedded Wafer Level Ball Grid Array (eWLB) Technology for System Integration. In IEEE CPMT Symposium, Tokyo, Japan, 24–26 Aug 2010.

    Google Scholar 

  149. Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel. 2007. The Redistributed Chip Package: A Breakthrough for Advanced Packaging. In IEEE 57th Electronic Components and Technology Conference, 286–291. Reno, NV, May 29–June 1 2007.

    Google Scholar 

  150. Hayes, S., N. Chhabra, T. Duong, Z. Gong, D. Mitchell, and J. Wright. 2011. System-in-Package Opportunities with the Redistributed Chip Package (RCP). In 8th Annual International Wafer-Level Packaging Conference, 10.1–10.7. Santa Clara, CA, 3–6 Oct 2011.

    Google Scholar 

  151. Lau, J.H. 2016. 3D IC Integration and Packaging. New York: McGraw-Hill Book Company.

    Google Scholar 

  152. Chaabouni, H., M. Rousseau, P. Ldeus, A. Farcy, R. El Farhane, A. Thuaire, G. Haury, A. Valentian, G. Billot, M. Assous, F. de Crecy, J. Cluzel, A. Toffoli, D. Bounchu, L. Cadix, T. Lacrevaz, P. Ancey, N. Sillon, and B. Flechet. 2010. Investigation on TSV Impact on 65 nm CMOS Devices and Circuits. In IEEE International Electron Devices Meeting, 35.1.1–35.1.4. San Francisco, CA, 6–8 Dec 2010.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ASM Pacific Technology, Hong Kong, New Territories, Hong Kong

    John H. Lau

Authors
  1. John H. Lau
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to John H. Lau .

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Lau, J.H. (2018). 3D Integration. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_10

Download citation

  • DOI: https://doi.org/10.1007/978-981-10-8884-1_10

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-8883-4

  • Online ISBN: 978-981-10-8884-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation