Abstract
The chapter discusses about RTL design and verification using Verilog. The RTL design and verification strategies are also discussed in this chapter. The chapter even discusses about the FSM performance improvement strategies. The chapter is useful to understand the role of the RTL design and verification engineer and important concepts.
The design and verification of large-density SOC consumes almost around 80% of the overall product cycle time.
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Taraate, V. (2019). RTL Design and Verification. In: Advanced HDL Synthesis and SOC Prototyping . Springer, Singapore. https://doi.org/10.1007/978-981-10-8776-9_4
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DOI: https://doi.org/10.1007/978-981-10-8776-9_4
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Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-8775-2
Online ISBN: 978-981-10-8776-9
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