Design and Implementation of Hamming Encoder and Decoder Over FPGA

Abstract

In the digital world, the field of communication has developed many applications. In most sectors of communication, the input message or data is encoded at the transmitter and transferred through the communication channel. Data is received at the receiver and after the decoding of the received data, original data is recovered successfully. Noise can be added to the communication channel. Noise affects the input data and data might get corrupted during the transmission. So it is essential for the receiver to have applied some functions, which are able to localize the error at the receiver end data. There are many types of forward error-correcting code. Hamming code is one of them, which has got numerous applications. Hamming error detection and correction code are used in many common applications, including optical storage devices, random access memory, wireless communication system, high-speed modems (ADSL, xDSL) and digital television system. This paper tries to elucidate the design process of hamming code using VLSI because FPGA is more cost-effective than the other system. In this paper, the algorithm for hamming code encoding and decoding has been discussed and after hamming error detection and correction code has been implemented in Verilogger pro 6.5 to get the results. Hamming code is an improved version compared to the parity check method and it is implemented in Verilog in which n-bit of information data is transmitted with (n − 1) redundancy bits. In order to find the value of these redundant bits, a hamming code is written in Verilog, which will be simulated in Xilinx software. The result of simulation and test bench waveforms is also explained.