Abstract
With the advent of globalization in the fabrication of IC (integrated circuits) industry, the threat of Hardware Trojan (HT) has increased. The malevolent HT inserted at unused resources and the user is unaware. We proposed a technique, i.e., the combination of modified BISA (Built In Self Authentication) and AES (Advance Encryption Standard) to protect the system from HT hazard. In modified BISA, the unused resources pins are filled with the dummy functional logic. Then the encryption is done by AES algorithm, the code is decrypted with the key that is known only to user. The proposed technique is implemented on Xilinx 10.1_ISE in family Automatic Sparton3 and device XA3S50. The scheme reduces the probability of HT insertion and performance remains same as of original circuitry.
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Brar, N.K., Dhindsa, A., Agrawal, S. (2019). Prevention of Hardware Trojan by Reducing Unused Pins and AES in FPGA. In: Sa, P., Bakshi, S., Hatzilygeroudis, I., Sahoo, M. (eds) Recent Findings in Intelligent Computing Techniques . Advances in Intelligent Systems and Computing, vol 707. Springer, Singapore. https://doi.org/10.1007/978-981-10-8639-7_11
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DOI: https://doi.org/10.1007/978-981-10-8639-7_11
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