Communication, Devices, and Computing pp 263-272 | Cite as

# Application of PSO Variants for Optimal Design of Two-Stage CMOS Op-amp with Robust Bias Circuit

## Abstract

This paper investigates the relative optimizing proficiency between two PSO alternatives, particularly craziness-based PSO (CRPSO) and PSO with an aging leader and challengers (ALC-PSO) for the design of two-stage CMOS op-amp with robust bias circuit. PSO is a very simple optimization algorithm, and it copies the communal manner of bird flocking. The main disadvantages of PSO are premature convergence and stagnation problem. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this paper, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE-based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported method for the design of the aforementioned circuit in terms of the MOS area, gain, and power dissipation, etc.

## Keywords

Analog IC CMOS two-stage op-amp PSO CRPSO ALC-PSO Robust bias## 1 Introduction

Exact sizing of MOS transistors in VLSI circuit is a complex process. Evolutionary technique is a proficient option for the automation of sizing of MOS transistors in analog IC. Eberhart et al. [1] have developed the concept of PSO. Symmetric switching CMOS inverter using PSOCFIWA is reported in [2]. Area of CMOS operational amplifier circuit [3, 4] is optimized by utilizing PSO technique. To obtain the maximum gain and UGB, folded cascode op-amp is designed by PSO method in [5].

Here, the area-optimized design of two-stage CMOS op-amp with robust bias circuit [6] is investigated by utilizing CRPSO [7] and ALC-PSO algorithm [8, 9, 10], individually.

The paper is written as follows: The steps for the design of the circuit are explained, and the cost function (CF) is described in Sect. 2. In Sect. 3, PSO, CRPSO, and ALC-PSO algorithms are described concisely. In Sect. 4, discussion of simulation results for the proposed techniques is given. Lastly, Sect. 5 concludes the paper.

## 2 Specifications for Design and Formulation of Cost Function

_{IC}

_{(min)}), maximum output voltage (V

_{out}

_{(max)}), phase margin \( \left( {\phi_{M} } \right) \).

_{L}). The steps for the design of the circuit [6] are given as follows:

- Step 1:
\( C_{C} = \frac{16kT}{{3\omega_{u} S_{n} \left( f \right)}}\left[ {1 + \frac{SR}{{\omega_{u} \left( {V_{DD} - V_{{IC\left( {\hbox{max} } \right)}} + V_{tn} } \right)}}} \right] \)

- Step 2:
\( I_{D7} = SR\left( {C_{C} + C_{L} } \right) \)

- Step 3:
\( L_{6} = \sqrt {\frac{{3\mu_{p} \left( {V_{DD} - V_{{out\left( {\hbox{max} } \right)}} } \right)C_{C} }}{{2\omega_{u} \left( {C_{C} + C_{L} } \right)\tan \left( {\phi_{M} } \right)}}} \)

- Step 4:
\( W_{6} = \frac{{2SR\left( {C_{C} + C_{L} } \right)}}{{\mu_{p} C_{ox} \left( {V_{DD} - V_{{out\left( {\hbox{max} } \right)}} } \right)^{2} }}L_{6} \)

- Step 5:
\( I_{D5} = C_{C} (SR) \)

- Step 6:
\( \frac{{W_{1} }}{{L_{1} }} = \frac{{W_{2} }}{{L_{2} }} = \frac{{\omega_{u}^{2} C_{C} }}{{\mu_{n} C_{ox} SR}} \)

- Step 7:
\( \frac{{W_{5} }}{{L_{5} }} = \frac{{W_{8} }}{{L_{8} }} = \frac{{2(SR)C_{C} }}{{\mu_{n} C_{ox} \left( {V_{{IC\left( {\hbox{min} } \right)}} - V_{SS} - V_{tn} - \frac{SR}{{\omega_{u} }}} \right)^{2} }} \)

- Step 8:
\( \frac{{W_{7} }}{{L_{7} }} = \left( {\frac{{C_{C} + C_{L} }}{{C_{C} }}} \right)\left( {\frac{{W_{5} }}{{L_{5} }}} \right) \)

- Step 9:
\( \frac{{W_{3} }}{{L_{3} }} = \frac{{W_{4} }}{{L_{4} }} = \frac{{\left( {\frac{{W_{6} }}{{L_{6} }}} \right)}}{{2\left( {\frac{{W_{7} }}{{L_{7} }}} \right)}}\left( {\frac{{W_{5} }}{{L_{5} }}} \right) \)

- Step 10:
\( \frac{{W_{9} }}{{L_{9} }} = \left( {\frac{{C_{C} }}{{C_{C} + C_{L} }}} \right)\left( {\frac{{W_{6} }}{{L_{6} }}} \right) \)

- Step 11:
\( \frac{{W_{10} }}{{L_{10} }} = \frac{{W_{11} }}{{L_{11} }} = \frac{{W_{12} }}{{L_{12} }} = \frac{{W_{13} }}{{L_{13} }} = \frac{{\left( {\frac{{W_{6} }}{{L_{6} }}} \right)}}{{\left( {\frac{{W_{7} }}{{L_{7} }}} \right)}}\left( {\frac{{W_{8} }}{{L_{8} }}} \right) \)

- Step 12:
\( \frac{{W_{14} }}{{L_{14} }} = 4\left( {\frac{{W_{8} }}{{L_{8} }}} \right) \)

- Step 13:
\( R_{B} = \frac{1}{{\sqrt {\left( {2\mu_{n} C_{ox} \left( {\frac{{W_{8} }}{{L_{8} }}} \right)C_{C} \left( {SR} \right)} \right)} }} \)

The number of transistors present in the circuit is 14. Here, CRPSO and ALC-PSO are individually applied for minimizing the CF.

## 3 Evolutionary Algorithms Used

In this section, PSO, CRPSO, and ALC-PSO are concisely presented. PSO is an optimization process dependent on population. PSO is a very simple method and is well explained in various literature [1, 2].

In birds’ flocking, a bird habitually modifies directions unexpectedly. PSO is altered by presenting a different velocity equation correlated with various random numbers and the “craziness velocity.” This altered PSO is called as CRPSO [7].

Different parameters used for ALC-PSO algorithm

Parameters | CRPSO | ALC-PSO |
---|---|---|

Population size (p) | 10 | 10 |

Dimension of the optimization problem (q) | 13 | 13 |

Iteration cycle | 100 | 100 |

\( C_{1} \) | 2 | 2 |

\( C_{2} \) | 2 | 2 |

\( P_{cr} \) | 0.3 | – |

\( v^{craziness} \) | 0.0001 | – |

Initial value of lifespan (Θ | – | 3 |

## 4 Discussions of Simulation Results

_{L}, R

_{B}, W

_{i}, and L

_{i}where i = 1, 2, …, 14. For the authentication purpose, Cadence specter software (IC 5.1.41) is used to perform the transistor-level simulations of the circuit.

Technology and inputs considered

Inputs, technology | Values taken |
---|---|

V | 2.5 |

V | −2.5 |

V | −0.901 |

V | 0.711 |

\( K_{n}^{{\prime }} \) (µA/V | 182 |

\( K_{p}^{{\prime }} \) (µA/V | 41.6 |

Technology | 0.5 µm |

with the input values of \( V_{DD} = 2.5\,{\text{V}},\,V_{SS} = - 2.5\,{\text{V}},\,V_{tn} = 0.711\,{\text{V}},\,V_{tp} = - 0.901\,{\text{V}},\,K_{n}^{{\prime }} = 182\,{\upmu }{\text{A}}/{\text{V}}^{2} ,\,K^{\prime}_{p} = 41.6\,{{\upmu}}{\text A}/{\text{V}}^{2} . \)

The design constraints are taken as \( C_{L} \le 10\,{\text{pF}},\,C_{C} = 0. 5\,{\text{pF,}}\, 0. 7 5\,{{\upmu}}{\text m} \le {\text{W}}_{\text{i}} \, \le 1 0 0\,{{\upmu}}\text{m},\, 0. 5\,{{\upmu}}{\text m} \le \,{\text{L}}_{\text{i}} \le 5\,{{\upmu}}\text{m}. \)

Constraints of the design parameters

Parameters | Ranges taken |
---|---|

SR (V/µs) | ≥5 |

f | ≥5 |

V | ≥ −2.25 |

V | ≤2.2 |

Phase margin (degree) | >60 |

C | ≤10 |

C | 0.5 |

L | 0.5 µm ≤ L |

W | 0.75 µm ≤ W |

Design variables attained by different techniques

Design variables | [6] | CRPSO | ALC-PSO |
---|---|---|---|

W | 1/1 | 1/1 | 1/1 |

W | 1/1 | 1/4 | 1/3 |

W | 1/3 | 1/2 | 1/2.2 |

W | 31/2.5 | 9.99/2.5 | 8/2.25 |

W | 3/1 | 5.7/1 | 4/1 |

W | 1/1 | 1/2 | 1/2.2 |

W | 1/1 | 1/2 | 1/2.2 |

W | 2.5/2 | 1.23/1 | 1.2/1 |

C | 0.5 | 0.5 | 0.5 |

C | 5 | 4.5 | 4.25 |

R | Not reported | 27.9 | 25 |

Mahattanakul et al. [6] have designed the similar circuit studied in this paper. The simulation results reported in [6] have SR of 6.21 V/µs, f_{u} of 6.15 MHz, gain of 85 dB, and total transistor area of 100.5 µm^{2}.

^{2}, respectively, as given in Table 5.

Comparison of performance specifications

Design criteria | Specifications | [6] | CRPSO | ALC-PSO |
---|---|---|---|---|

C | ≤10 | 5 | 4.5 | 4.25 |

SR (V/µs) | ≥5 | 6.21 | 5.2474 | 13.437 |

Power dissipation (µW) | <350 | Not reported | 347.5 | 342.5 |

Phase margin (º) | >60 | 65 | 68.56 | 66.56 |

Unity gain frequency (MHz) | ≥5 | 6.15 | 11.2 | 12.2 |

Gain (dB) | >80 | 85 | 80.61 | 85.02 |

V | ≥ −2.25 | −2.2 | −1.593 | −1.615 |

V | ≤2.25 | 2 | 1.474 | 1.732 |

V | ≥ −2.2 | −2.15 | −2 | −2.1 |

V | ≤2.2 | 2.15 | 2 | 1.98 |

CMRR (dB) | >70 | Not reported | 90.36 | 96.36 |

PSRR | >70 | Not reported | 110.1 | 84.58 |

PSRR | >70 | Not reported | 83.86 | 106.9 |

Propagation delay (µs) | <1 | Not reported | 0.183 | 0.171 |

Input-referred noise @1 MHz \( ({{nV} \mathord{\left/ {\vphantom {{nV} {\sqrt {Hz} }}} \right. \kern-0pt} {\sqrt {Hz} }}) \) | \( < 45 \) | 44 | 39.85 | 38.85 |

Total MOS area (µm | <101 | 100.5 | 55.905 | 46.6 |

_{u}of 12.2 MHz, gain of 85.02 dB, and total transistor area of 46.6 µm

^{2}. So, ALC-PSO technique produces the most promising results for SR, UGB, gain, and the total transistor area. ALC-PSO-based simulation results for the circuit obtained from SPICE are presented in Figs. 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11, respectively.

## 5 Conclusions

In this paper, two-stage CMOS op-amp with robust bias circuit is optimally designed by utilizing the CRPSO and ALC-PSO, individually. Both the CRPSO and ALC-PSO are proficient to generate the design optimal design variables. Simulations in SPICE environment have been executed by using the design variables obtained from CRPSO and ALC-PSO, individually. SPICE simulation results establish that evolutionary technique-based design meets all the specifications as well as reduce the total transistor area. ALC-PSO shows to be the best optimizer for the designed circuit under consideration. Future scope would be to explore the optimization efficiency of other metaheuristic methods for analog VLSI circuit sizing issues.

## References

- 1.J. Kennedy, R. Eberhart, Particle swarm optimization, in
*Proceedings of the IEEE International Conference on Neural Network*, vol. 4 (1995), pp. 1942–1948Google Scholar - 2.B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, Design of symmetric switching CMOS inverter using PSOCFIWA, in
*Proceedings of the IEEE ICCSP’ 14*, pp. 1818–1824, 3–5 April 2014, Melmaruvathur, Tamil Nadu, IndiaGoogle Scholar - 3.R.A. Vural, T. Yildirim, Analog circuit sizing via swarm intelligence. AEU Int. J. Electron. Commun.
**66**(9), 732–740 (2012)CrossRefGoogle Scholar - 4.R.A. Vural, T. Yildirim, Swarm intelligence based sizing methodology for CMOS operational amplifier, in
*Proceedings of the 12th IEEE Symposium on Computational Intelligence and Informatics*(2011), pp. 525–528Google Scholar - 5.V. Ceperic, Z. Butkovic, A. Baric, Design and optimization of self-biased complementary folded cascode, in
*Proceedings of the IEEE Mediterranean Electrotechnical Conference (MELECON)*(2006), pp. 145–148Google Scholar - 6.J. Mahattanakul, J. Chutichatuporn, Design procedure for two-stage CMOS opamp with flexible noise power balancing scheme. IEEE Trans. Circuits Syst.
**52**(8), 1508–1514 (2005)CrossRefGoogle Scholar - 7.B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, Optimal analog active filter design using craziness based particle swarm optimization algorithm. Int. J. Numer. Model.: Electron. Netw. Devices Fields
**28**(5), 593–609 (2015)CrossRefGoogle Scholar - 8.B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, PSO with aging leader and challengers for optimal design of high speed symmetric switching CMOS inverter. Int. J. Mach. Learn. Cybern.
**8**, 1403–1422 (2017)CrossRefGoogle Scholar - 9.B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm. Int. J. Mach. Learn. Cybern.
**7**(2), 325–344 (2016)CrossRefGoogle Scholar - 10.B.P. De, R. Kar, D. Mandal, S.P. Ghoshal, Particle swarm optimization with aging leader and challengers for optimal design of analog active filters. Circuits Syst. Signal Process.
**34**(3), 707–737 (2015)CrossRefGoogle Scholar - 11.R.J. Baker, H.W. Li, D.E. Boyce,
*CMOS Circuit Design, Layout, and Simulation*(Wiley Interscience, New York, 1998)Google Scholar