Abstract
This paper investigates the relative optimizing proficiency between two PSO alternatives, particularly craziness-based PSO (CRPSO) and PSO with an aging leader and challengers (ALC-PSO) for the design of two-stage CMOS op-amp with robust bias circuit. PSO is a very simple optimization algorithm, and it copies the communal manner of bird flocking. The main disadvantages of PSO are premature convergence and stagnation problem. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this paper, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE-based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported method for the design of the aforementioned circuit in terms of the MOS area, gain, and power dissipation, etc.
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De, B.P., Maji, K.B., Chowdhury, D., Kar, R., Mandal, D., Ghoshal, S.P. (2017). Application of PSO Variants for Optimal Design of Two-Stage CMOS Op-amp with Robust Bias Circuit. In: Bhaumik, J., Chakrabarti, I., De, B.P., Bag, B., Mukherjee, S. (eds) Communication, Devices, and Computing. ICCDC 2017. Lecture Notes in Electrical Engineering, vol 470. Springer, Singapore. https://doi.org/10.1007/978-981-10-8585-7_25
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DOI: https://doi.org/10.1007/978-981-10-8585-7_25
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