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Application of PSO Variants for Optimal Design of Two-Stage CMOS Op-amp with Robust Bias Circuit

  • Bishnu Prasad De
  • K. B. Maji
  • Dibyendu Chowdhury
  • R. Kar
  • D. Mandal
  • S. P. Ghoshal
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 470)

Abstract

This paper investigates the relative optimizing proficiency between two PSO alternatives, particularly craziness-based PSO (CRPSO) and PSO with an aging leader and challengers (ALC-PSO) for the design of two-stage CMOS op-amp with robust bias circuit. PSO is a very simple optimization algorithm, and it copies the communal manner of bird flocking. The main disadvantages of PSO are premature convergence and stagnation problem. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this paper, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE-based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported method for the design of the aforementioned circuit in terms of the MOS area, gain, and power dissipation, etc.

Keywords

Analog IC CMOS two-stage op-amp PSO CRPSO ALC-PSO Robust bias 

1 Introduction

Exact sizing of MOS transistors in VLSI circuit is a complex process. Evolutionary technique is a proficient option for the automation of sizing of MOS transistors in analog IC. Eberhart et al. [1] have developed the concept of PSO. Symmetric switching CMOS inverter using PSOCFIWA is reported in [2]. Area of CMOS operational amplifier circuit [3, 4] is optimized by utilizing PSO technique. To obtain the maximum gain and UGB, folded cascode op-amp is designed by PSO method in [5].

Here, the area-optimized design of two-stage CMOS op-amp with robust bias circuit [6] is investigated by utilizing CRPSO [7] and ALC-PSO algorithm [8, 9, 10], individually.

The paper is written as follows: The steps for the design of the circuit are explained, and the cost function (CF) is described in Sect. 2. In Sect. 3, PSO, CRPSO, and ALC-PSO algorithms are described concisely. In Sect. 4, discussion of simulation results for the proposed techniques is given. Lastly, Sect. 5 concludes the paper.

2 Specifications for Design and Formulation of Cost Function

The circuit shown in Fig. 1 is optimally designed by using CRPSO and ALC-PSO, individually. The specifications for design are taken as follows: slew rate (SR), unity gain frequency \( \left( {\omega_{u} } \right) \), minimum ICMR (VIC (min)), maximum output voltage (Vout (max)), phase margin \( \left( {\phi_{M} } \right) \).
Fig. 1

Two-stage CMOS op-amp with robust bias circuit

The variables taken for the design are given as follows: width of channel (W) and length of channel (L) for the transistors present in the circuit, load capacitance (CL). The steps for the design of the circuit [6] are given as follows:
  1. Step 1:

    \( C_{C} = \frac{16kT}{{3\omega_{u} S_{n} \left( f \right)}}\left[ {1 + \frac{SR}{{\omega_{u} \left( {V_{DD} - V_{{IC\left( {\hbox{max} } \right)}} + V_{tn} } \right)}}} \right] \)

     
  2. Step 2:

    \( I_{D7} = SR\left( {C_{C} + C_{L} } \right) \)

     
  3. Step 3:

    \( L_{6} = \sqrt {\frac{{3\mu_{p} \left( {V_{DD} - V_{{out\left( {\hbox{max} } \right)}} } \right)C_{C} }}{{2\omega_{u} \left( {C_{C} + C_{L} } \right)\tan \left( {\phi_{M} } \right)}}} \)

     
  4. Step 4:

    \( W_{6} = \frac{{2SR\left( {C_{C} + C_{L} } \right)}}{{\mu_{p} C_{ox} \left( {V_{DD} - V_{{out\left( {\hbox{max} } \right)}} } \right)^{2} }}L_{6} \)

     
  5. Step 5:

    \( I_{D5} = C_{C} (SR) \)

     
  6. Step 6:

    \( \frac{{W_{1} }}{{L_{1} }} = \frac{{W_{2} }}{{L_{2} }} = \frac{{\omega_{u}^{2} C_{C} }}{{\mu_{n} C_{ox} SR}} \)

     
  7. Step 7:

    \( \frac{{W_{5} }}{{L_{5} }} = \frac{{W_{8} }}{{L_{8} }} = \frac{{2(SR)C_{C} }}{{\mu_{n} C_{ox} \left( {V_{{IC\left( {\hbox{min} } \right)}} - V_{SS} - V_{tn} - \frac{SR}{{\omega_{u} }}} \right)^{2} }} \)

     
  8. Step 8:

    \( \frac{{W_{7} }}{{L_{7} }} = \left( {\frac{{C_{C} + C_{L} }}{{C_{C} }}} \right)\left( {\frac{{W_{5} }}{{L_{5} }}} \right) \)

     
  9. Step 9:

    \( \frac{{W_{3} }}{{L_{3} }} = \frac{{W_{4} }}{{L_{4} }} = \frac{{\left( {\frac{{W_{6} }}{{L_{6} }}} \right)}}{{2\left( {\frac{{W_{7} }}{{L_{7} }}} \right)}}\left( {\frac{{W_{5} }}{{L_{5} }}} \right) \)

     
  10. Step 10:

    \( \frac{{W_{9} }}{{L_{9} }} = \left( {\frac{{C_{C} }}{{C_{C} + C_{L} }}} \right)\left( {\frac{{W_{6} }}{{L_{6} }}} \right) \)

     
  11. Step 11:

    \( \frac{{W_{10} }}{{L_{10} }} = \frac{{W_{11} }}{{L_{11} }} = \frac{{W_{12} }}{{L_{12} }} = \frac{{W_{13} }}{{L_{13} }} = \frac{{\left( {\frac{{W_{6} }}{{L_{6} }}} \right)}}{{\left( {\frac{{W_{7} }}{{L_{7} }}} \right)}}\left( {\frac{{W_{8} }}{{L_{8} }}} \right) \)

     
  12. Step 12:

    \( \frac{{W_{14} }}{{L_{14} }} = 4\left( {\frac{{W_{8} }}{{L_{8} }}} \right) \)

     
  13. Step 13:

    \( R_{B} = \frac{1}{{\sqrt {\left( {2\mu_{n} C_{ox} \left( {\frac{{W_{8} }}{{L_{8} }}} \right)C_{C} \left( {SR} \right)} \right)} }} \)

     
The size of initial population matrix is p × q, (p = 10 and q = 13). Rows (p) indicate the particle vectors present in the population. Columns (q) indicate the dimensions of particle vector and are denoted as
$$ \begin{aligned} & Y = [SR,\,\omega_{u} ,V_{IC(\hbox{min} )} ,\,V_{out(\hbox{max} )} ,\,\phi_{M} ,\,C_{L} ,\,L_{1} ,\,L_{3} ,\,L_{5} ,\, \\ & L_{7} ,\,L_{9} ,\,L_{10} ,\,L_{14} ]. \\ \end{aligned} $$
Therefore, the total number of variables to be optimized is q = 13. The area taken by all the transistors in the circuit is defined as cost function (CF) and is represented in (1).
$$ CF = \sum\limits_{i = 1}^{14} {(W_{i} \times L_{i} )} $$
(1)

The number of transistors present in the circuit is 14. Here, CRPSO and ALC-PSO are individually applied for minimizing the CF.

3 Evolutionary Algorithms Used

In this section, PSO, CRPSO, and ALC-PSO are concisely presented. PSO is an optimization process dependent on population. PSO is a very simple method and is well explained in various literature [1, 2].

In birds’ flocking, a bird habitually modifies directions unexpectedly. PSO is altered by presenting a different velocity equation correlated with various random numbers and the “craziness velocity.” This altered PSO is called as CRPSO [7].

Idea of aging leader and challengers is introduced in the PSO to avoid premature convergence by producing challengers when current leader gets entrapped into local optima. ALC-PSO algorithm is well described in [8, 9, 10]. Parameters of CRPSO and ALC-PSO algorithm are provided in Table 1.
Table 1

Different parameters used for ALC-PSO algorithm

Parameters

CRPSO

ALC-PSO

Population size (p)

10

10

Dimension of the optimization problem (q)

13

13

Iteration cycle

100

100

\( C_{1} \)

2

2

\( C_{2} \)

2

2

\( P_{cr} \)

0.3

\( v^{craziness} \)

0.0001

Initial value of lifespan (Θ0)

3

4 Discussions of Simulation Results

MATLAB is used to implement the CRPSO and ALC-PSO techniques to design the circuit (Fig. 1). The input variables are shown in Table 2. CRPSO and ALC-PSO are individually applied to attain the values of CL, RB, Wi, and Li where i = 1, 2, …, 14. For the authentication purpose, Cadence specter software (IC 5.1.41) is used to perform the transistor-level simulations of the circuit.
Table 2

Technology and inputs considered

Inputs, technology

Values taken

VDD (V)

2.5

VSS (V)

−2.5

Vtp (V)

−0.901

Vtn (V)

0.711

\( K_{n}^{{\prime }} \) (µA/V2)

182

\( K_{p}^{{\prime }} \) (µA/V2)

41.6

Technology

0.5 µm

CRPSO and ALC-PSO are employed to design the circuit considering the constraints as
$$ SR \ge 5\,{\text{V}}/\upmu{\text{s}},f_{u} \ge 5\,{\text{MHz}},\,V_{{IC\left( {\hbox{min} } \right)}} \ge - 2.25,\,V_{{out\left( {\hbox{max} } \right)}} \le 2.2,\,\phi_{M} > 60^{^\circ } $$

with the input values of \( V_{DD} = 2.5\,{\text{V}},\,V_{SS} = - 2.5\,{\text{V}},\,V_{tn} = 0.711\,{\text{V}},\,V_{tp} = - 0.901\,{\text{V}},\,K_{n}^{{\prime }} = 182\,{\upmu }{\text{A}}/{\text{V}}^{2} ,\,K^{\prime}_{p} = 41.6\,{{\upmu}}{\text A}/{\text{V}}^{2} . \)

The design constraints are taken as \( C_{L} \le 10\,{\text{pF}},\,C_{C} = 0. 5\,{\text{pF,}}\, 0. 7 5\,{{\upmu}}{\text m} \le {\text{W}}_{\text{i}} \, \le 1 0 0\,{{\upmu}}\text{m},\, 0. 5\,{{\upmu}}{\text m} \le \,{\text{L}}_{\text{i}} \le 5\,{{\upmu}}\text{m}. \)

Process technology parameter used is 0.5 µm HP’S CMOS 14 TB [11]. The previously stated inputs and the constraints of the design parameters are given in Tables 2 and 3, respectively.
Table 3

Constraints of the design parameters

Parameters

Ranges taken

SR (V/µs)

≥5

fu (MHz)

≥5

VIC(min) (V)

≥ −2.25

Vout (max) (V)

≤2.2

Phase margin (degree)

>60

CL (pF)

≤10

CC (pF)

0.5

Li (µm)

0.5 µm ≤ Li ≤ 5 µm

Wi (µm)

0.75 µm ≤ Wi ≤ 100 µm

The optimal design variables attained by utilizing CRPSO and ALC-PSO, individually, are given in Table 4. Using the design variables, the circuit is re-designed in SPICE environment to obtain the specifications of the design.
Table 4

Design variables attained by different techniques

Design variables

[6]

CRPSO

ALC-PSO

W1/L1; W2/L2 (µm/µm)

1/1

1/1

1/1

W3/L3; W4/L4 (µm/µm)

1/1

1/4

1/3

W5/L5; W8/L8 (µm/µm)

1/3

1/2

1/2.2

W6/L6 (µm/µm)

31/2.5

9.99/2.5

8/2.25

W7/L7 (µm/µm)

3/1

5.7/1

4/1

W9/L9 (µm/µm)

1/1

1/2

1/2.2

W10/L10–W13/L13 (µm/µm)

1/1

1/2

1/2.2

W14/L14 (µm/µm)

2.5/2

1.23/1

1.2/1

Cc (pF)

0.5

0.5

0.5

CL (pF)

5

4.5

4.25

RB (kΩ)

Not reported

27.9

25

Mahattanakul et al. [6] have designed the similar circuit studied in this paper. The simulation results reported in [6] have SR of 6.21 V/µs, fu of 6.15 MHz, gain of 85 dB, and total transistor area of 100.5 µm2.

CRPSO method results in slew rate, unity gain frequency, gain, and total transistor area of 5.2474 V/µs, 11.2 MHz, 80.61 dB, and 55.905 µm2, respectively, as given in Table 5.
Table 5

Comparison of performance specifications

Design criteria

Specifications

[6]

CRPSO

ALC-PSO

CL (pF)

≤10

5

4.5

4.25

SR (V/µs)

≥5

6.21

5.2474

13.437

Power dissipation (µW)

<350

Not reported

347.5

342.5

Phase margin (º)

>60

65

68.56

66.56

Unity gain frequency (MHz)

≥5

6.15

11.2

12.2

Gain (dB)

>80

85

80.61

85.02

VIC (min) (V)

≥ −2.25

−2.2

−1.593

−1.615

VIC (max) (V)

≤2.25

2

1.474

1.732

Vout(min) (V)

≥ −2.2

−2.15

−2

−2.1

Vout (max) (V)

≤2.2

2.15

2

1.98

CMRR (dB)

>70

Not reported

90.36

96.36

PSRR+ (dB)

>70

Not reported

110.1

84.58

PSRR (dB)

>70

Not reported

83.86

106.9

Propagation delay (µs)

<1

Not reported

0.183

0.171

Input-referred noise @1 MHz \( ({{nV} \mathord{\left/ {\vphantom {{nV} {\sqrt {Hz} }}} \right. \kern-0pt} {\sqrt {Hz} }}) \)

\( < 45 \)

44

39.85

38.85

Total MOS area (µm2)

<101

100.5

55.905

46.6

ALC-PSO technique results in SR of 13.437 V/µs, fu of 12.2 MHz, gain of 85.02 dB, and total transistor area of 46.6 µm2. So, ALC-PSO technique produces the most promising results for SR, UGB, gain, and the total transistor area. ALC-PSO-based simulation results for the circuit obtained from SPICE are presented in Figs. 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11, respectively.
Fig. 2

Plot of SR

Fig. 3

Plot of power dissipation

Fig. 4

Plot of UGB, gain, and phase

Fig. 5

Plot of ICMR

Fig. 6

Plot of output voltage swing

Fig. 7

Plot of CMRR

Fig. 8

Plot of positive PSRR

Fig. 9

Plot of negative PSRR

Fig. 10

Plot of delay

Fig. 11

Plot of noise

5 Conclusions

In this paper, two-stage CMOS op-amp with robust bias circuit is optimally designed by utilizing the CRPSO and ALC-PSO, individually. Both the CRPSO and ALC-PSO are proficient to generate the design optimal design variables. Simulations in SPICE environment have been executed by using the design variables obtained from CRPSO and ALC-PSO, individually. SPICE simulation results establish that evolutionary technique-based design meets all the specifications as well as reduce the total transistor area. ALC-PSO shows to be the best optimizer for the designed circuit under consideration. Future scope would be to explore the optimization efficiency of other metaheuristic methods for analog VLSI circuit sizing issues.

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Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • Bishnu Prasad De
    • 1
  • K. B. Maji
    • 2
  • Dibyendu Chowdhury
    • 1
  • R. Kar
    • 2
  • D. Mandal
    • 2
  • S. P. Ghoshal
    • 3
  1. 1.Department of ECEHITHaldiaIndia
  2. 2.Department of ECENIT DurgapurDurgapurIndia
  3. 3.Department of EENIT DurgapurDurgapurIndia

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