Post-layout Power Supply Noise Suppression and Performance Analysis of Multi-core Processor Using 90 nm Process Technology

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 470)

Abstract

This article deals with accurate budget and placement of decoupling capacitance (decap) based on the supply noise. Decaps are placed near the noisy modules and effectively reduce the supply drop. The novelty of this paper lies in exhaustive estimation of Ldi/dt drop and IR drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay, and noise performance to its best. In this work, the suppression in supply noise, power consumption. and propagation delay parameters with decap allocation for 512-point FFT core are investigated and satisfactory results are obtained.

Keywords

Decoupling capacitor (decap) FFT processor Power supply noise (PSN) Power distribution network (PDN) Application-specific integrated circuit (ASIC) 

Notes

Acknowledgements

This work is supported by Advanced VLSI Design Laboratory, IIT Kharagpur.

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Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringBrainware Group of Institutions-S.D.E.T.Barasat, KolkataIndia
  2. 2.Department of Electronics and Communication EngineeringHaldia Institute of TechnologyHaldiaIndia

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