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Static Power Modeling for Modern Processor

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Energy Efficient High Performance Processors

Abstract

Power and energy estimation tools are essential tools that are used by system designers, software developers, and compiler developers to optimize their products. In this work, we present a novel method for statically estimating and analyzing the energy and power of programs, the method gives power and energy statistics on the feasible program paths for both the core and cache using symbolic execution. Unlike profile-guided optimizations—that require generating stimulus and running them on the target processor to cover all possible paths—or the dataflow analysis that traverse all control flow graph paths, our method traverses all feasible paths of the program. Our method is static, which enables running it at compile-time. We demonstrated how the tool can be used to optimize the power and energy of programs at compile-time by choosing compiler flags that minimize the energy or power of the program.

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Notes

  1. 1.

    In this work, we assume that the cycles per LLVM instruction (C) are constant for all instructions.

  2. 2.

    There might be leakage or dynamic power that is consumed by the cache regardless of the executed instruction at the core, this depends on the cache power management implementation.

  3. 3.

    More details in cache emulator section.

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Correspondence to Jawad Haj-Yahya .

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Haj-Yahya, J., Mendelson, A., Ben Asher, Y., Chattopadhyay, A. (2018). Static Power Modeling for Modern Processor. In: Energy Efficient High Performance Processors. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-8554-3_5

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  • DOI: https://doi.org/10.1007/978-981-10-8554-3_5

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