Abstract
Power and energy estimation tools are essential tools that are used by system designers, software developers, and compiler developers to optimize their products. In this work, we present a novel method for statically estimating and analyzing the energy and power of programs, the method gives power and energy statistics on the feasible program paths for both the core and cache using symbolic execution. Unlike profile-guided optimizations—that require generating stimulus and running them on the target processor to cover all possible paths—or the dataflow analysis that traverse all control flow graph paths, our method traverses all feasible paths of the program. Our method is static, which enables running it at compile-time. We demonstrated how the tool can be used to optimize the power and energy of programs at compile-time by choosing compiler flags that minimize the energy or power of the program.
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Notes
- 1.
In this work, we assume that the cycles per LLVM instruction (C) are constant for all instructions.
- 2.
There might be leakage or dynamic power that is consumed by the cache regardless of the executed instruction at the core, this depends on the cache power management implementation.
- 3.
More details in cache emulator section.
References
Cadar, Cristian, Daniel Dunbar, and Dawson R. Engler. “KLEE: Unassisted and Automatic Generation of High-Coverage Tests for Complex Systems Programs.” OSDI. Vol. 8. 2008.
V. Tiwari, et al., “Instruction Level Power Analysis and Optimization of Software,” in Journals of VLSI Signal Processing Systems, 1996, pp. 223–233.
King, James C. “Symbolic execution and program testing.” Communications of the ACM 19.7 (1976): 385–394.
M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks With On-Chip Decoupling Capacitors. New York: Springer, 2008.
Reddi, Vijay Janapa, et al. “Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling.” Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on. IEEE, 2010.
Reddi, Vijay Janapa, et al. “Voltage emergency prediction: Using signatures to reduce operating margins.” High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on. IEEE, 2009.
McCurdy, Collin, Gabriel Marin, and Jeffrey S. Vetter. “Characterizing the impact of prefetching on scientific application performance.” High Performance Computing Systems. Performance Modeling, Benchmarking and Simulation. Springer International Publishing, 2014. 115–135.
Lefurgy, Charles R., et al. “Active management of timing guardband to save energy in POWER7.” proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2011.
Haj-Yihia, Jawad, et al. “Compiler-directed power management for superscalars.” ACM Transactions on Architecture and Code Optimization (TACO) 11.4 (2015): 48.
Een, Niklas, and Niklas Sörensson. “MiniSat: A SAT solver with conflict-clause minimization.” Sat 5 (2005).
Anand, Saswat, Patrice Godefroid, and Nikolai Tillmann. “Demand-driven compositional symbolic execution.” Tools and Algorithms for the Construction and Analysis of Systems. Springer Berlin Heidelberg, 2008. 367–381.
Ma, Kin-Keung, et al. “Directed symbolic execution.” Static Analysis. Springer Berlin Heidelberg, 2011. 95–111.
Staats, Matt, and Corina Pǎsǎreanu. “Parallel symbolic execution for structural test generation.” Proceedings of the 19th international symposium on Software testing and analysis. ACM, 2010.
Grech, Neville, et al. “Static analysis of energy consumption for LLVM IR programs.” Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems. ACM, 2015.
Lattner, Chris, and Vikram Adve. “LLVM: A compilation framework for lifelong program analysis & transformation.” Code Generation and Optimization, 2004. CGO 2004. International Symposium on. IEEE, 2004.
Shao, Yakun Sophia, and David Brooks. “Energy characterization and instruction-level energy model of Intel’s Xeon Phi processor.” Proceedings of the International Symposium on Low Power Electronics and Design. IEEE Press, 2013.
Coreutils. www.gnu.org/software/coreutils.
Borghesi, Andrea, et al. “Power Capping in High Performance Computing Systems.” Principles and Practice of Constraint Programming. Springer International Publishing, 2015.
Hönig, Timo, et al. “SEEP: exploiting symbolic execution for energy-aware programming.” Proceedings of the 4th Workshop on Power-Aware Computing and Systems. ACM, 2011.
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3, Section 14.9 (as of August 2014).
David, H., Gorbatov, E., Hanebutte, U.R., et al.: RAPL: memory power estimation and capping. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 189–194. IEEE (2010).
S. Chattopadhyay and A. Roychoudhury. Scalable and precise refinement of cache timing analysis via path-sensitive verification. Real-Time Systems, 49(4), 2013.
C. Ferdinand and R. Wilhelm. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems, 17(2–3):131–181, 1999.
Wagemann, Peter, et al. “Worst-case energy consumption analysis for energy-constrained embedded systems.” Proceedings of the 27th Euromicro Conference on Real-Time Systems (ECRTS). IEEE, 2015.
Hönig, Timo, et al. “Proactive energy-aware programming with PEEK.” 2014 Conference on Timely Results in Operating Systems (TRIOS 14). USENIX, 2014.
Brooks, David, and Vivek Tiwari. “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations.” (2000).
W. Ye, N. Vijaykrishnam, M. Kandemir, and M. Irwin. The design and use of simplepower: a cycle accurate energy estimation tool. In Proc. Design Automation Conference DAC’00, June 2000.
Haj-Yihia, J., Yasin, A., Asher, Y.B. and Mendelson, A., 2016. Fine-grain power breakdown of modern out-of-order cores and its implications on Skylake-based systems. ACM Transactions on Architecture and Code Optimization (TACO), 13(4), p. 56.
Chen, Yang, Yuanjie Huang, Lieven Eeckhout, Grigori Fursin, Liang Peng, Olivier Temam, and Chengyong Wu. “Evaluating iterative optimization across 1000 datasets.” ACM Sigplan Notices 45, no. 6 (2010): 448–459.
Eeckhout, Lieven, Hans Vandierendonck, and Koenraad De Bosschere. “Workload design: Selecting representative program-input pairs.” In Parallel Architectures and Compilation Techniques, 2002. Proceedings. 2002 International Conference on, pp. 83–94. IEEE, 2002.
Cammarota, Rosario, Alexandru Nicolau, Alexander V. Veidenbaum, Arun Kejariwal, Debora Donato, and Mukund Madhugiri. “On the determination of inlining vectors for program optimization.” In International Conference on Compiler Construction, pp. 164–183. Springer Berlin Heidelberg, 2013.
Fursin, Grigori, Renato Miceli, Anton Lokhmotov, Michael Gerndt, Marc Baboulin, Allen D. Malony, Zbigniew Chamski, Diego Novillo, and Davide Del Vento. “Collective mind: Towards practical and collaborative auto-tuning.” Scientific Programming 22, no. 4 (2014): 309–329.
Kadayif, Ismail, M. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, and Anand Sivasubramaniam. “Compiler-directed high-level energy estimation and optimization.” ACM Transactions on Embedded Computing Systems (TECS) 4, no. 4 (2005): 819–850.
Gustaffson, Jan, Andreas Ermedahl, and Björn Lisper. “Algorithms for infeasible path calculation.” In OASIcs-OpenAccess Series in Informatics, vol. 4. Schloss Dagstuhl-Leibniz-Zentrum für Informatik, 2006.
Lam, Patrick, Eric Bodden, Ondrej Lhoták, and Laurie Hendren. “The Soot framework for Java program analysis: a retrospective.” In Cetus Users and Compiler Infastructure Workshop (CETUS 2011), vol. 15, p. 35. 2011.
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Haj-Yahya, J., Mendelson, A., Ben Asher, Y., Chattopadhyay, A. (2018). Static Power Modeling for Modern Processor. In: Energy Efficient High Performance Processors. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-8554-3_5
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DOI: https://doi.org/10.1007/978-981-10-8554-3_5
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