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Energy Efficient High Performance Processors pp 107–133Cite as

Compiler-Directed Energy Efficiency

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Abstract

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building power delivery network for the worst-case power consumption is not energy efficient and often impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this work, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

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Author information

Authors and Affiliations

  1. School of Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore

    Jawad Haj-Yahya

  2. Department of Computer Science Department, Technion—Israel Institute of Technology, Haifa, Israel

    Avi Mendelson

  3. Department of Computer Science, University of Haifa, Haifa, Israel

    Yosi Ben Asher

  4. School of Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

Authors
  1. Jawad Haj-Yahya
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  2. Avi Mendelson
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  3. Yosi Ben Asher
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  4. Anupam Chattopadhyay
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Corresponding author

Correspondence to Jawad Haj-Yahya .

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Haj-Yahya, J., Mendelson, A., Ben Asher, Y., Chattopadhyay, A. (2018). Compiler-Directed Energy Efficiency. In: Energy Efficient High Performance Processors. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-8554-3_4

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  • DOI: https://doi.org/10.1007/978-981-10-8554-3_4

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-8553-6

  • Online ISBN: 978-981-10-8554-3

  • eBook Packages: EngineeringEngineering (R0)

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