Design and Development of Digital Energy Meter on FPGA
Nowadays, microprocessors and microcontrollers are widely used in the field of modern power system schemes. But these devices are slow due to their sequential approach. Field Programmable Gate Array (FPGA) works on concurrent architecture and advantage of reusability. Time delay constraint is a crucial factor in different applications of modern power system schemes such as relays, energy meters, and Phasor Measurement Unit (PMU). In this paper, different FPGA-based modules are implemented which work on pipelined architecture instead of traditional microprocessors and microcontrollers which are sequential in nature. Time delay in the sense, process, and communication cycles is reduced due to concurrent working modules of the FPGA. In this paper, various FPGA modules are implemented on GENESYS XILINX VIRTEX 5 XC5VLX50T FPGA Board for implementing digital energy meter. Modules are implemented in Very High Speed Integrated Circuit Hardware Descriptive Language (VHDL) with the help of different Intellectual Property (IP) cores. Test results are presented and communicated to the hyper-terminal.
KeywordsAnalog to Digital Converter (ADC) Concurrent Architecture FPGA Modules IP Cores Zero Crossing Detector (ZCD)
Authors gratefully thank Dr. M. K. Rawat (Principal, Faculty of Engineering and Technology (F.E.T), Agra College, Agra); Dr. R. K. Srivastava (Convener F.E.T), Agra College; Dr. V. K. Jain, (Dept. of Physics, F.E.T, Agra College, Agra); Er. Amit Srivastava, (Department of Electronics and Communication, F.E.T, Agra College, Agra); and Er. Amit Bhatnagar, (Department of Mathematics, F.E.T, Agra College, Agra) for their support and precious guidance. Authors are also thankful to the technical assistant Mr. Praveen Sharma for his valuable help.
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