Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA

  • Rashmi Sharma
  • Bishwajeet Pandey
  • Vikas Jha
  • Siddharth Saurabh
  • Sweety Dabas
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)


This paper illustrates the behavior of the UART in response to the various I/O standards. Research has been carried out to find out the most ideal standard for UART design which would thereby minimize the losses. Increase in power is seen as the frequency and capacitance for a standard are increased. When a relative analysis is done for the different I/O standards, it has been found out that LVCMOS18 consumes the least power and hence is the most efficient I/O standard for the UART design. Increment in power consumption has been observed within a percentage of 99.73–40% for a capacitance of 5 pF and 99.64–54.54% for a capacitance value of 50 pF. XILINX software and Verilog Hardware Description Language have been used for this purpose. The behavior for various standards has been studied to get the most energy-efficient design for the UART. This would help in increasing the output from the UART, thereby proving to be a boon in the field of electronics where power consumption is a major issue.


Input Output Standard Energy efficient UART 90 nm FPGA 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Rashmi Sharma
    • 1
  • Bishwajeet Pandey
    • 1
  • Vikas Jha
    • 1
  • Siddharth Saurabh
    • 2
  • Sweety Dabas
    • 3
  1. 1.Gyancity Research LabGurgaonIndia
  2. 2.Giant Meterwave Radio TelescopeKhodad, PuneIndia
  3. 3.Maharaja Surajmal InstituteJanakpuriIndia

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