Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA

  • Vandana Thind
  • Sujeet Pandey
  • D. M. Akbar Hussain
  • Bhagwan Das
  • M. F. L. Abdullah
  • Bishwajeet Pandey
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)

Abstract

In this work, we are going to implement DES algorithm on 28-nm Artix-7 FPGA. To achieve high-performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst-case slack, maximum delay, setup time, hold time, and data skew path. The cases on which analysis is done are like worst-case slack, best-case achievable, timing error, and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis, there is maximum of 19.56% of variation in worst-case slack, 0.29% change for best-case achievable, 41.17% change in timing error, and 64.12% change in timing score for two different frequencies. From this work, we also notified the delays during various signals; accordingly, we have designed our own algorithm with strong security encryption.

Keywords

Timing constraints DES algorithm 28-nm FPGA Pin-out report Mapping report Minimum period Maximum performance Static timing analysis 

1 Introduction

In this particular paper, we have worked on the pin-out report and timing analysis of DES algorithm at two different frequencies, i.e., 2.4 and 3.6 GHz. This analysis gives us detailed report about timing delay, slack, worst-case achievement, timing score, and timing errors. Slack is the difference between the required time and arrival time of signal between each connection. Worst-case achievement means maximum delay countered in our algorithm. The timing score refers to the total value constitutes the timing analysis for all constraints and by how much the constraints are failing in picoseconds where the “sum” (in picoseconds) has not met any timing constrained value at each unique endpoint. Timing score is calculated by the fact: It is equal to the sum of absolute value of all worst-case negative slack of each failing unique endpoint in picoseconds. Timing error is variation in original signal with given period of time. In this research work, we have done analysis on pin-out report, which contains detailed report about the placement of input/output data pins and operating/reference voltages on the bank of Artix-7 FPGA. We have also notified the static timing analysis, which is useful for evaluating the performance of each path, where certain violations are considered like setup time violation, when the input signal reaches late, i.e., after the clock signal is active, and hold time violation means the input signal reaches earlier than the expected time. In static timing analysis, we have considered two paths: setup and hold, where the analysis of data path delay and clock skew path for different checks like min period, min low pulse, min high pulse, setup, and hold is done. Min period is the time constraint on the clock net which generates a check for delays. From all the analyses, we notified the percentage change in all the timing constraints of different checks. This also shows us if we change frequency for DES algorithm how much variation we get.

2 Related Work

A researcher had analyzed the algorithm in perspective of total time and power utilized by DES algorithm [1], whereas we have done complete analysis on timing constraints of time delay, slack, worst-case achievement, timing score, and timing error [1]. One designer had researched on security of key bits in 16-rounded DES [2], and we have researched on complete detail of DES algorithm’s pin-out report using high-performance software Xilinx [2]. Another researcher had worked on the past and future scope in addition with environmental effects [3], whereas we have done analysis on effect of timing conditions on DES algorithm at two different frequencies, i.e., 2.4 and 3.6 GHz [3]. Some researcher had tested the optimization of 4-rounded DES algorithms [4], whereas we have tested DES algorithm with 16-rounded DES algorithms [4]. One scientist had done analysis on the implementation of cryptographic algorithms on FPGA [5, 6, 7] with speed grade-4 [8] whereas we have done our analysis on Artix-7 FPGA with speed grade-3 [8]. Some other researcher had focused on bit slice architecture of DES algorithm [8], whereas here we have done complete analysis on registers and HDL synthesis of DES algorithm.

3 Pin-out Report

Pin-out report specifies the location of pseudo-component on the module when a net connects from one pin on module to a pin on another module. This report gives the detail about data of particular bit to be placed on which particular pin according to the logic of algorithm. For this particular DES algorithm, detailed pin-out report is given in the following tables. Input/output bank number is type of layout of IC with basically consisting of pin where we can provide different voltages to our board without any complication. These tables basically show us position of different data bits of plaintext, ciphertext, VCCO, reference voltages, and mixed signal voltages.

In Table 1, 64-bit plaintext is placed on different pin numbers, which are situated on different input/output banks, i.e., banks 35 and 14 of Artix-7 FPGA.
Table 1

Pin-out report for 64-bit input data of DES algorithm

Pin number

Signal name

Data of bit

I/O bank number

A4

Plaintext

61

35

B2,B3

Plaintext

62,64

35

D2,D3

Plaintext

51,30

35

E2,E3

Plaintext

58,54

35

F4

Plaintext

25

35

G2,G6

Plaintext

52,60

35

H5

Plaintext

56

35

J2,J4

Plaintext

57,26

35

K17,K18

Plaintext

63,27

14

L6,L13,L14,L15,L16,L18

Plaintext

36,53,28,59,31,32

14

M14,M16,M17,M18

Plaintext

29,43,44,33

14

N14,N15,N16,N17

Plaintext

39,45,46,41

14

P14,P15,P17,P18

Plaintext

40,1,47,42

14

R10-R13,R15-R18

Plaintext

24,55,34,35,2,5,48,37

14

T9-T16,T18

Plaintext

22,23,13,20,3,4,6,38

14

U3,U4,U12-U14,U16-U18

Plaintext

49,50,14,21,18,11,9,10

14

V10-V17

Plaintext

16,17,15,19,7,8,12

14

Table 2 gives the detailed pin-out report for 64-bit ciphertext which is basically encrypted output data of DES algorithm. We get ciphertext from banks 35 and 15.
Table 2

Pin-out report for 64-bit output data of DES algorithm

Pin number

Signal name

Data of bit

I/O bank number

A1,A3,A5,A6,A11,A13-A16,A18

Ciphertext

51,54,59,64,32,41,44,39,42,46

35,15

B1,B4,B6,B7,B11-14,B16-18,B15

Ciphertext

53,40,61,63,33,30,29,28,55,52,43

35,15

C4,C7,C12,C14-17

Ciphertext

38,57,31,27,50,16,17

35,15

D4,D8,D12,D13,D15,D17,D18

Ciphertext

2,62,37,36,47,10,18

35,15

E5-7,E15-18

Ciphertext

34,56,58,45,1,7,22

35,15

F3,F13-16,F18

Ciphertext

48,35,60,3,6,24

35,15

G14,G16-18

Ciphertext

8,4,14,21

15

H14-17

Ciphertext

5,13,49,11

15

J13-15,J17,J18

Ciphertext

12,15,25,20,23

15

K13,K15,K16

Ciphertext

9,26,19

15

Table 3 gives positions of pins which act as input as operating voltages which is provided to different sections of our Artix-7 FPGA board. Maximum of 1.50 VCCO is provided to DES algorithm.
Table 3

Pin-out report for different operating voltages in DES algorithm

Pin number

Signal name

I/O bank number

Voltages

B10

VCCO_16

35

1.50

A17

VCCO_15

15

1.50

B10

VCCO_16

16

ANY

C3

VCCO_35

35

1.50

C13

VCCO_15

15

1.50

D6

VCCO_35

35

1.50

D16

VCCO_15

15

0.75

F2

VCCO_35

35

1.50

G5

VCCO_35

35

1.50

G15

VCCO_15

15

1.50

J1

VCCO_35

35

1.50

K4

VCCO_34

34

ANY

K14

VCCO_15

15

1.50

L17

VCCO_14

14

ANY

N3

VCCO_34

34

ANY

N13

VCCO_14

14

ANY

P6

VCCO_34

34

ANY

P16

VCCO_34

14

ANY

R9

VCCO_0

0

ANY

T2

VCCO_34

34

ANY

T12

VCCO_14

14

ANY

U5

VCCO_14

14

ANY

U15

VCCO_14

14

ANY

Table 4 reports us that 0.75 V is used as reference voltages, and maximum of six pins is provided with reference voltages. Table 5 mentions four mixed signals like clock, reset, address, chip select bar used in DES algorithm. Bank numbers used for these signals are 35 and 34.
Table 4

Pin-out report for reference voltages provided to DES algorithm

Pin number

Signal name

I/O bank number

Voltages

D7

VREF

35

0.75

F6

VREF

35

0.75

L5

VREF

34

0.75

M13

VREF

14

0.75

R5

VREF

34

0.75

U11

VREF

14

0.75

Table 5

Pin-out for mixed signal used in DES algorithm

Pin number

Signal name

I/O bank number

D5

CLK

35

F5

RST

35

V2

ADDRESS

34

U2

CHIP SELECT BAR

34

4 Timing Analysis

This research notifies us details about time constraint of slack, worst-case achievement, best-case achievable, timing errors, and timing score. In this particular research, we have taken into consideration different checks like setup, hold, minimum period, minimum low, and high pulse, where we analyzed the percentage change of above-mentioned cases, at two different frequencies, i.e., 2.4 and 3.6 GHz.

Tables 6 and 7 give the amount of worst-case slack, best-case achievable, timing errors, and timing score for setup, hold, min period, min low pulse, and min high pulse checks. It is basically a timing analysis on DES algorithm at two different frequencies: 2.4 and 3.6 GHz. Percentage change in above-mentioned cases is detailed below, along with figures carrying the comparison of time constraint of different cases at different frequencies.
Table 6

Timing constraint of DES algorithm at 2.4 GHz frequency

Check

Worst-case slack

Best-case achievable

Timing errors

Timing score

Setup

−2.105 ns

2.521 ns

1440

1,405,879

Hold

−0.121

 

34

1633

Min period

−1.176 ns

1.592 ns

1025

599,192

Min low pulse

−0.584 ns

1.000 ns

1024

598,016

Min high pulse

−0.584 ns

1.000 ns

2048

11,906,032

Table 7

Timing constraint of DES algorithm at 3.6 GHz frequency

Check

Worst-case slack

Best-case achievable

Timing errors

Timing score

Setup

−2.315 ns

2.521 ns

1440

1,678,687

Hold

−0.081

 

20

586

Min period

−1.315 ns

1.592 ns

1025

741,667

Min low pulse

−0.726 ns

1.003 ns

1024

744,062

Min high pulse

−0.726 ns

1.003 ns

2048

1,488,124

4.1 Worst-Case Slack in Timing Analysis of DES Algorithm

Figure 1 shows the changes of time constraint of different cases at two frequencies, i.e., 2.4 and 3.6 GHz. Percentage change of worst-case slack in setup check, hold check, min period, min low pulse, and min high pulse is 9.97, 49.38, 10.57 and 19.56 respectively.
Fig. 1

Comparison of worst-case slack at two different frequencies

4.2 Best Achievable Time in Timing Analysis of DES Algorithm

Figure 2 shows that there is no percentage change in setup, hold, and min period checks for both frequencies, but there is 0.29% of change in min low pulse and min high pulse check.
Fig. 2

Comparison of best-case achievable time at two frequencies

4.3 Timing Errors in Timing Analysis of DES Algorithm

Figure 3 shows that only hold check varies by 41.17% and rest of checks remain unchanged.
Fig. 3

Comparison of timing errors for two different frequencies

4.4 Timing Scores in Timing Analysis of DES Algorithm

Figure 4 shows that from two different frequencies setup, check changes by 16.25%, hold check varies by 64.12%, min period check changes by 19.21%, and both min low pulse check and min high pulse check vary by 19.62%.
Fig. 4

Comparison of timing scores for two different frequencies

5 Static Timing Analysis

In static timing analysis, we examined the difference in setup paths and hold paths. We have taken three sources and destinations; considering them, we have varied slack, data path delay, and skew clock path. Following tables show different reading of setup paths and hold paths at two different frequencies: 2.4 and 3.6 GHz. In these analyses, a total of 3840 paths, 1440 endpoints, 5232 connections were analyzed by Xilinx software.

5.1 Setup Paths in Static Timing Analysis

From this observation, we found that setup path basically faces setup time violation, which means the signal arrives at destination too late than the time it should reach there. In Tables 8 and 9, we have done analysis on slack, data skew delay, and skew clock path, for three paths with maximum values.
Table 8

Static timing analysis on setup paths at 2.4 GHz frequency

Source

Destination

Slack

Data path delay

Skew clock path

Reg1_26

Reg1_22

−2.105

2.225

−0.261

Reg1_24

Reg1_22

−2.031

2.151

−0.261

Reg1_25

Reg1_22

−1.815

1.935

−0.261

Table 9

Static timing analysis on setup paths at 3.6 GHz frequency

Source

Destination

Slack

Data path delay

Skew clock path

Reg1_10

Reg1_10

−2.219

2.200

−0.261

Reg1_8

Reg1_30

−2.089

2.069

−0.262

Reg1_8

Reg1_16

−2.274

2.254

−0.262

Table 8 accords us with report for static timing analysis on setup path at 2.4 GHz frequency, where maximum slack has maximum data path delay and skew clock is almost the same for all three paths but in very less terms.

Table 9 subsidizes that when static timing analysis was done at 3.6 GHz frequency, for minimum slack, it is observed that data path delay (DPD) is minimum and skew clock path (SCP) is maximum.

This analysis for both frequencies is shown in Fig. 5.
Fig. 5

Slack, data path skew, and skew clock path of setup paths

5.2 Hold Paths in Static Timing Analysis

Similar to setup path, hold path also suffers hold time violation which means that the clock signal changes earlier as soon as the clock signal gets active. Here also, analysis has been done on two different frequencies as shown in Table 10.
Table 10

Static timing analysis on hold paths at 2.4 GHz frequency

Source

Destination

Slack

Data path delay

Skew clock path

Reg1_29 right

Reg1_29 left

−0.121

0.250

0.371

Reg1_23 left

Reg1_23right

−0.119

0.251

0.370

Reg1_23 right

Reg1_23 left

−0.104

0.265

0.369

On observing Table 10, we see that in hold path, for maximum slack, there is minimum data path delay and maximum skew clock path.

Table 11 notifies that at 3.6 GHz frequency, for hold paths, maximum slack has minimum data path delay and minimum skew clock path. This analysis for both frequencies is shown in Fig. 6.
Table 11

Static timing analysis on hold paths at 3.6 GHz frequency

Source

Destination

Slack

Data path delay

Skew clock path

Reg1_4 left

Reg1_4 right

−0.081

0.289

0.370

Reg1_32right

Reg1_32left

−0.051

0.356

0.407

Reg1_15left

Reg1_32right

−0.042

0.364

0.400

Fig. 6

Slack, data path skew, and skew clock path of hold paths

5.3 Component Switching Limits

Component switching analysis insures us that the operating voltage is supplied to the device within the range specified by the device. In this particular analysis, we analyzed the slack, limit, and check values.

From Tables 12 and 13, we noticed that for both frequencies, slack, value, and limit do not vary for min low and high pulse check; there is variation in values when we increase the frequency, i.e., 2.4–3.6 GHz; therefore, percentage change in this value is 19.6, 33.65, and 0% for slack, value, and limit, respectively.
Table 12

Component switching report at 2.4 GHz frequency

Check

Slack

Value

Limit

Min period

−1.176

0.416

1.592

Min low pulse

−0.584

0.208

0.500

Min high pulse

−0.584

0.208

0.500

Table 13

Component switching report at 3.6 GHz frequency

Check

Slack

Value

Limit

Min period

−1.315

0.277

1.592

Min low pulse

−0.727

0.138

0.500

Min high pulse

−0.727

0.138

0.500

6 Timing Report

In timing report, we examined the clock information report which tells us that at clock signal CLK, clock buffer loads the signal of quantity 1024. It also shows that speed grade of design is −3 and minimum period of design is 1.980 ns where maximum frequency is 504.974 MHz, minimum input arrival time before clock is 2.213 ns, minimum output required time after clock is 0.640 ns.

7 Mapping Report

Mapping report gives us the analysis of timing constraint, of placement and routing of components on FPGA.

In Tables 14 and 15, we analyzed the mapping report of DES algorithm at two different frequencies, i.e., 2.4 and 3.6 GHz. In this analysis, we noticed the amount of worst-case slack, best-case achievement, timing error, and timing score for five different checks. Mapping report gives us report of timing analysis which is done directly from the placement and routing of the components on the board.
Table 14

Mapping report of DES algorithm at 2.4 GHz frequency

Check

Worst-case slack (ns)

Best-case achievement

Timing error

Timing score

Setup

−0.379

0.795 ns

960

138,768

Hold

0.069

0

0

Min period

−1.176

1.592 ns

1025

599,192

Min low pulse

−0.584

1.000 ns

1024

598,016

Min high pulse

−0.584

1.000 ns

2048

1,196,032

Table 15

Mapping report of DES algorithm at 3.6 GHz frequency

Check

Worst-case slack (ns)

Best-case achievement

Timing error

Timing score

Setup

−0.518

0.795 ns

1440

334,128

Hold

0.069

0

0

Min period

−1.315

1.592 ns

1025

741,667

Min low pulse

−0.726

1.003 ns

1024

744,062

Min high pulse

−0.726

1.003 ns

2048

1,488,124

7.1 Worst-Case Slack in Mapping Report of DES Algorithm

In Fig. 7, we analyzed that worst-case slack is 26.8% and there is no change for hold check. Min period check, min low pulse check, and min high pulse check vary by 10.5 and 19.5 respectively.
Fig. 7

Component switching limit for two different frequencies

7.2 Best-Case Achievement in Mapping Report of DES Algorithm

In Fig. 8, infers that best-case achievement varies only for min low pulse check and min high pulse check, i.e., by 0.299% both. For rest of the check, there is no variation.
Fig. 8

Variation in worst-case slack from mapping report

7.3 Timing Errors in Mapping Report of DES Algorithm

In Fig. 9, we analyzed that setup check changes by 33.33% from 2.4 to 3.6 GHz frequency. For other checks, there is no variation in timing errors.
Fig. 9

Variation in best-case achievement from mapping report

7.4 Timing Score in Mapping Report of DES Algorithm

In Fig. 10, variation in timing score of setup check is 58.46%, and min period check, min low pulse check, and min high pulse check vary by 19.21, 19.62, and 19.62%, respectively. There is no change for hold check (Fig. 11).
Fig. 10

Variation in timing errors from mapping report

Fig. 11

Variation in timing score from mapping report

8 Generating Clock Report

In this analysis, we analyzed the amount of change in net skew and max skew of DES algorithm at two different frequencies. The difference between the loads driven by the net is called skew. Max skew is the timing constraint used to control the amount of skew on a net (Table 16).
Table 16

Comparison of clock report at two different frequencies

Clock net (GHz)

Fan-out

Net skew

Max

2.4

407

0.185

1.300

3.6

405

0.237

1.353

In Fig. 12, we noticed that there is 21.94% change in the net skew and 3.91% variation in the max skew between two different frequencies 2.4 and 3.6 GHz.
Fig. 12

Net skew and max skew for two different frequencies

9 Conclusion

We conclude that in timing analysis, maximum changes compared to all timing constraint are found for min high pulse check, for both frequencies and hold check does not have best-case achievable.

Timing score is maximum setup check. After this, we did static timing analysis report, which infers that in setup path performance, for maximum slack, data path delay is maximum. In hold path performance, for maximum slack, we calculated maximum delay. In component switching limit, slack is maximum for min period check. With increase in frequency, low pulse and high pulse decrease. In mapping report, we can reduce the slack by interchanging worst-case slack of min high pulse by min period. Hold check does not vary for any of the cases; it remains constant.

10 Future Scope

In this particular research, we have implemented our research of timing constraint analysis on the Artix-7 FPGA, whereas in near future, we can use vertex-8, vertex-9, RC5, RC6, RC7, etc. Here, we have done timing analysis by which we come to know about the changes of different timing constraint on the two different frequencies; in near future, we can do its power analysis, from where we can eventually get idea of time and power aspects of DES algorithm. Power and timing analysis could help us replacing FPGA with any newer IC which would then come into existence to obtain better results.

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Vandana Thind
    • 1
  • Sujeet Pandey
    • 2
  • D. M. Akbar Hussain
    • 3
  • Bhagwan Das
    • 4
  • M. F. L. Abdullah
    • 4
  • Bishwajeet Pandey
    • 2
  1. 1.School of Electronics and ElectricalChitkara UniversityChandigarhIndia
  2. 2.Gyancity Research LabJammuIndia
  3. 3.Aalborg UniversityEsbjergDenmark
  4. 4.UTHMParit RajaMalaysia

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