Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA

  • Tarun Agrawal
  • Vivek Srivastava
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 732)


In this paper, we are designing an efficient memory using LVCMOS and HSTL-I IO Standards on 28 nm (Artix-7) FPGA. There are various families, LVCMOS and HSTL-I families are compared for finding the maximum power-efficient IO standards between them. We tested 64-bit RAM circuit at different range of frequencies of Intel Processor that are at Intel I-3 5005U 2.0 GHz, Intel I-3, 5015U 2.1 GHz, Intel I-3 5157U 2.5 GHz, Intel I-5 3380M 2.9 GHz, Intel I-5 3340U 3.1 GHz, and Intel I-7 3370K 3.5 GHz frequency range to find the most power-efficient circuit. When we migrate our design to LVCMOS from HSTL, then there is 40–60% saving in power dissipation of memory circuits.


Artix-7 Efficient energy RAM Less power LVCMOS HSTL-I Filed programming gate array (FPGA) 


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© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and CommunicationG.L.A. UniversityMathuraIndia

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