A Novel Energy-Efficient Hybrid Full Adder Circuit

  • Trapti SharmaEmail author
  • Laxmi Kumre
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 38)


This article presents a novel energy-efficient hybrid one-bit full adder cell employing modified GDI logic and transmission gate logic. To analyze the performance of various circuits, simulations were carried out using Synopsys HSPICE tool taking 45-nm technology model. Full-swing differential XOR–XNOR circuits with restoration transistors are employed in order to realize a noise-resistant full adder circuit. The weak restoration transistors at the intermediate outputs of XOR–XNOR ensure the reduced static power dissipation together with the usage of low power transmission gates at the output side leads to overall reduction in power of the proposed circuit. Comprehensive experiment results illustrate the superiority of the proposed adder in terms of power–delay product (PDP) over the other existing designs with regard to the different simulation conditions such as supply power scaling, load, temperature, and frequency variations.


Hybrid full adder Low power Energy efficient VLSI design 



This work has been done from the Grant Received from Visvesvaraya PhD Scheme for Electronics and IT.


  1. 1.
    Sabaghi M, Marjani S, Majdabadi A (2016) The design of ultra-low power adder cell in 90 and 180 nm CMOS technology. Circuits Syst 7(2):58–67Google Scholar
  2. 2.
    Wariya S, Nagaria R, Tiwari S (2012) Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design. VLSI Design 1–18Google Scholar
  3. 3.
    Jiang Y, Al-Sheraidah A, Wang Y, Sha E, Chung J-G (2004) A novel multiplexer-based low-power full adder. IEEE Trans Circuits Syst II 51(7):345–348CrossRefGoogle Scholar
  4. 4.
    Wang D, Yang M, Cheng W, Guan X, Zhu Z, Yang Y (2009) Novel low power full adder cells in 180 nm CMOS technology. ICIEA 1:0Google Scholar
  5. 5.
    Zimmermann R, Fichtner W (1997) Low-power logic styles. IEEE J Solid State Circuit 32:1079–1090CrossRefGoogle Scholar
  6. 6.
    Pashaki ER, Shalchian M (2016) Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI. Integr VLSI J 55:194–201CrossRefGoogle Scholar
  7. 7.
    Weste NHE, Eshraghian K (1988) Principles of CMOS VLSI design: a system perspective. Addison-Wesley, ReadingGoogle Scholar
  8. 8.
    Morgenshtein A, Fish A, Wagner IA (2002) Gate diffusion input (GDI)-A power efficient method for digital combinatorial circuits. IEEE Trans VLSI Syst 10(5):566–581CrossRefGoogle Scholar
  9. 9.
    Morgenshtein A, Shwartz I, Fish A (2010) Gate diffusion input (GDI) logic in standard CMOS nanoscale process. In: Proceedings of the IEEE 26-th convention of electrical and electronics engineers in IsraelGoogle Scholar
  10. 10.
    Chowdhury SR, Banerjee A, Roy A, Saha H (2008) A high speed 8 transistor full adder design using novel 3 transistor XOR gates. Int J Electron Circuits Syst II:217–223Google Scholar
  11. 11.
    Shoba M, Nakkeeran R (2016) GDI based full adders for energy efficient arithmetic applications. Eng Sci Technol Int J 19:485–496CrossRefGoogle Scholar
  12. 12.
    Aguirre-Hernandez M, Linares-Aranda M (2011) CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans Very Larg Scale Integr (VLSI) Syst 19(4):718–721CrossRefGoogle Scholar
  13. 13.
    Foroutan V, Taheri M, Navi K, Mazreah A (2014) Design of two low power full adder cells using GDI structure and hybrid CMOS logic style. Integration (Amst) 47(1):48–61CrossRefGoogle Scholar
  14. 14.
    Uma R, Dhavachelvan P (2012) Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits. In: Proceedings of ICCCS, pp. 74–81CrossRefGoogle Scholar
  15. 15.
    Bhattacharyya P, Kundu B, Ghosh S, Kumar V, Dandapat A (2015) Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans Very Larg Scale Integr (VLSI) Syst 23(10):2001–2008 OctCrossRefGoogle Scholar
  16. 16.
    Goel S, Kumar A, Bayoumi M (2006) Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(12):1309–1321CrossRefGoogle Scholar
  17. 17.
    Belgacem H, Chiraz K, Rached T (2012) A novel differential XOR-based self-checking adder. Int J Electron 99(9):1239–1261CrossRefGoogle Scholar
  18. 18.
    F. Moradi, D.T. Wisland, H. Mahmoodi, S. Aunet, T.V. Cao, A. Peiravi, Ultra low power full adder topologies, in: Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3158–3161, May 2009Google Scholar
  19. 19.
    Shalem R, John E, John L.K (2002) A novel low power energy recovery full adder cell. In: Proceedings IEEE great lakes VLSI Symposium, pp. 380–383Google Scholar
  20. 20.
    Morgenshtein A, Shwartz I, Fish A (2014) Full swing gate diffusion input (GDI) logic case study for low power CLA adder design. Integr VLSI J 47(1):62–70CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of ECEMaulana Azad National University of TechnologyBhopalIndia

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