A Novel Energy-Efficient Hybrid Full Adder Circuit
This article presents a novel energy-efficient hybrid one-bit full adder cell employing modified GDI logic and transmission gate logic. To analyze the performance of various circuits, simulations were carried out using Synopsys HSPICE tool taking 45-nm technology model. Full-swing differential XOR–XNOR circuits with restoration transistors are employed in order to realize a noise-resistant full adder circuit. The weak restoration transistors at the intermediate outputs of XOR–XNOR ensure the reduced static power dissipation together with the usage of low power transmission gates at the output side leads to overall reduction in power of the proposed circuit. Comprehensive experiment results illustrate the superiority of the proposed adder in terms of power–delay product (PDP) over the other existing designs with regard to the different simulation conditions such as supply power scaling, load, temperature, and frequency variations.
KeywordsHybrid full adder Low power Energy efficient VLSI design
This work has been done from the Grant Received from Visvesvaraya PhD Scheme for Electronics and IT.
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