Novel Approach for Sleep Transistor Sizing to Suppress Power and Ground Bouncing Noise in MTCMOS Clustering Technique

Abstract

As the critical dimensions of MOSFETS are continuously shrinking, to achieve the high speed at present technology supply voltage is a challenging task for VLSI designers. At low supply voltage, maintain the high speed of integrated circuit and low-power dissipation is the major challenge for circuit designers. MTCMOS is the most useful technique for leakage power reduction in VLSI circuits. MTCMOS has some limitations in terms of delay and area due to extra SLEEP transistors. Area penalty at MTCMOS can be overcome by using a clustering technique, where a single SLEEP transistor is used for a number of integrated circuit cells. By proper sizing of sleep transistor in the cluster, it will overcome delay and area penalty in MTCMOS circuits with low leakage current. In this paper, we propose a technique for selecting proper sizing of sleep transistor for cell cluster under defined/marginal delay penalty. The proposed technique is tested on basic inverter cells circuit and from simulation results, we by properly sized SLEEP transistor achieve the high speed of operation and it is improved 2X times compared to conventional MTCMOS circuit. Here, we have also considered ground bouncing and power bouncing noise, and reduction in both is observed in the simulation result.