Abstract
This paper presents an overview of a reaction timer having an accuracy up to two decimal places (which is extendable). Three decade counters constitute the circuitry of this reaction timer wherein each of the decade counters is connected to four master–slave J-K flip-flops to form a sequential circuit. A delay signal is also introduced at the input so that the output is genuine. The whole simulation process is carried out in Cadence virtuoso analog and digital design environment of gpdk045 nm CMOS technology at a supply voltage of 1 V.
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Acknowledgements
Authors are thankful to Prof. V. R. Gupta HOD ECE, Prof. T. Ghosh Dean Sponsored Research, Prof. R. Sukesh Kumar Dean Faculty Affairs, and Prof. M. K. Mishra Vice-Chancellor, BIT Mesra Ranchi for providing infrastructure facility to carry out this research work. Authors are also thankful to RESPOND ISRO for funding this project.
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Bohra, V. et al. (2019). Design and Implementation of a Reaction Timer Using CMOS Logic. In: Nath, V., Mandal, J. (eds) Proceeding of the Second International Conference on Microelectronics, Computing & Communication Systems (MCCS 2017). Lecture Notes in Electrical Engineering, vol 476. Springer, Singapore. https://doi.org/10.1007/978-981-10-8234-4_43
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DOI: https://doi.org/10.1007/978-981-10-8234-4_43
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