Abstract
This paper presents the accomplishment of depleted power 32-bit RISC (reduced instruction set computer) processor using MIPS architecture with five-stage pipelining. Intention of the RISC processor is to do small set of instruction in order to enhance the processor speed. It includes five pipeline stages; they are instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM) and write back (WB) stages. Different sub-blocks employed are data memory (DM), register file, ALU and instruction memory (IM). Intention of the paper is to increase the operation and to decrease the power wastage of processor by clock gating technique. The proposed RISC processor design is implemented in Verilog-HDL. Module functionality, area and power dissipation are analysed using XILINX 14.7 ISE simulator and Spartan 6 family and has 45 nm technology.
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Mangalwedhe, S., Kulkarni, R., Kulkarni, S.Y. (2019). Low Power Implementation of 32-Bit RISC Processor with Pipelining. In: Nath, V., Mandal, J. (eds) Proceeding of the Second International Conference on Microelectronics, Computing & Communication Systems (MCCS 2017). Lecture Notes in Electrical Engineering, vol 476. Springer, Singapore. https://doi.org/10.1007/978-981-10-8234-4_27
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DOI: https://doi.org/10.1007/978-981-10-8234-4_27
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