Abstract
MOSFET is replaced by the best adaptable nanodevice, Carbon Nanotubes Field-Effect Transistor (CNTFET) for low-power, small area and delay-optimized VLSI circuit design [1, 2]. In this paper, a dual supply-stacked CNTFET SRAM cell is designed. The performance of 6T CNTFET SRAM cell, stack CNTFET SRAM cell and dual supply-stacked CNTFET SRAM cell is observed by calculating performance metrics of the memory cell such as static power and Static Noise Margin (SNM). From the simulation, it is observed that dual supply stack CNTFET SRAM cell static power is 15.8% lesser, SNM is 1.8% higher than stacked CNTFET SRAM. SNM improvement of 9.62% and static power reduction of 46.92% is obtained in dual supply-stacked CNTFET SRAM cell than 6T CNTFET SRAM cell. Simulation is carried out using Stanford University 32 nm CNTFET model invoked in CADENCE EDA tool.
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Elangovan, M., Gunavathi, K. (2019). High Stability and Low-Power Dual Supply-Stacked CNTFET SRAM Cell. In: Saini, H., Singh, R., Patel, V., Santhi, K., Ranganayakulu, S. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 33. Springer, Singapore. https://doi.org/10.1007/978-981-10-8204-7_21
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DOI: https://doi.org/10.1007/978-981-10-8204-7_21
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