Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders

  • M. Lokesh ChowdaryEmail author
  • A. Mallaiah
  • A. Jaya Lakshmi
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 33)


In many digital signal processors and different applications, the massive role is played by the multiplier. In any VLSI design mainly power, area and speed play a massive role, by improving any of these parameters the overall performance will be improved. Array multipliers and Tree multipliers are various types of multipliers, among those Wallace tree multiplier belongs to Tree multiplier which is better than booth multiplier in terms of speed, area, design complexity. Different existing approaches had been developed for the reduction of partial products. One of the existing approaches uses full adders and half adders in Wallace tree multiplier, but by using this approach number of stages would be increased when higher order multiplication is considered. To overcome this, an approach is proposed which includes 4:2 compressors & parallel prefix adders in Wallace tree multiplier design.


Wallace tree multiplier 4:2 compressors Brent–Kung adder Sparse Kogge-Stone adder 


  1. 1.
    Bais K, Ali Z (2016) Design of a high-speed Wallace tree multiplier. Int J Eng Sci Res Technol 5(6) (June 2016)Google Scholar
  2. 2.
    Jaiswal KB, Nithish Kumar V, Seshadri P, Lakshminarayanan G (2015) Low power Wallace tree multiplier using modified full adder. In: 2015 3rd international conference on signal processing, communication and networking (ICSCN)Google Scholar
  3. 3.
    George JP, Ramesh P (2015) Wallace tree multiplier using compressor. Int J Curr Eng Technol 5(3) (June 2015)Google Scholar
  4. 4.
    Padmajarani SV, Muralidhar M (2012) A new approach to implement parallel prefix adders in an FPGA. Int J Eng Res Appl (IJERA) 2(4):1524–1528 (July–August 2012)Google Scholar
  5. 5.
    Sreenivasa Goud E, Praveen Kumar PC (2013) Design and characterization of Sparse Kogge stone parallel prefix adder using FPGA. Int J Sci Eng Technol Res 02(06):467–479 (July 2013)Google Scholar
  6. 6.
    Dhivya C, Thiruppathi M, Sowmiya R (2015) Design of 8x8 Wallace multiplier using mux based full adder with compressor. Int Res J Eng Technol (Irjet) 02 (08 Nov 2015)Google Scholar
  7. 7.
    Kumar P, Kaur J (2014) Design of modified parallel prefix knowles adder. Int J Sci Res (IJSR) 3(7) (July 2014)Google Scholar
  8. 8.
    Potdukhe PP, Jaiswal VD (2016) Design of high speed carry select adder using Brent Kung adder. In: International conference on electrical, electronics, and optimization techniques (ICEEOT)—2016Google Scholar
  9. 9.
    Nair S, Khade RH, Saraf A (2015) Design and analysis of various 32 bit multipliers in an approach towards a fast multiplier. Int J Adv Res Electr Electron Instrum Eng 4(7) (July 2015)Google Scholar
  10. 10.
    Swathi AC, Yuvraj T, Praveen J, Raghavendra Rao A (2016) A novel modified low power Wallace tree multiplier using full and half adder. Int J Innov Res Electr Electron Instrum Control Eng 4(5) (May 2016)Google Scholar
  11. 11.
    Kaur JK (2013) Structural VHDL implementation of Wallace multiplier. Int J Sci Eng Res 4(4) (April 2013)Google Scholar
  12. 12.
    Bansal H, Sharma KG, Sharma T (2014) Wallace tree multiplier designs: a performance comparison. Innov Syst Des Eng 5(5)Google Scholar
  13. 13.
    Rani G, Kumar S (2014) Delay analysis of parallel-prefix adders. Int J Sci Res (IJSR) 3(6) (June 2014)Google Scholar
  14. 14.
    Rani G, Kumar S (2014) Delay analysis of parallel-prefix adders. Int J Sci Res (IJSR) 3(6) (June 2014)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • M. Lokesh Chowdary
    • 1
    Email author
  • A. Mallaiah
    • 1
  • A. Jaya Lakshmi
    • 2
  1. 1.Gudlavalleru Engineering CollegeGudlavalleruIndia
  2. 2.Vardhaman College of EngineeringHyderabadIndia

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