A Synoptic Study on Fault Testing in Reversible and Quantum Circuits

  • Ramyadeep Dey
  • Paramita Bandyopadhyay
  • Somenath Chandra
  • Ritajit Majumdar
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 88)

Abstract

Reversible computation, whose special class is quantum computation, arises from the desire to reduce power dissipation, which can be zero under ideal physical circumstances. Nowadays, error correction and fault testing are of utmost importance for the physical implementation of reversible and quantum circuits in a noisy environment. In this paper, we review various fault models in reversible and quantum circuits. In classical reversible circuits, we review (i) test pattern generation for Single Missing Gate Fault (SMGF), Partial Missing Gate Fault (PMGF), and Multiple Missing Gate Fault (MMGF) models and (ii) show that Universal Test Set (UTS) can be used to detect any of these faults. However, classical fault models do not capture all the logical failures found in quantum circuits. In quantum circuits, we review (i) depolarizing faults, initialization inaccuracy and measurement inaccuracy, and (ii) give some remedial strategies to deal with these fault models. Finally, we show that for a special class of quantum operators, detection of SMGF is sufficient to detect fault due to multiple occurrences of the gate also. Further, we argue with an example that it may not be possible to generate test patterns to detect any arbitrary SMGF in a quantum circuit.

Keywords

Fault testing Reversible circuits Quantum circuits 

References

  1. 1.
    Barrett, M.D., Schätz, T., Chiaverini, J., Leibfried, D., Britton, J., Itano, W.M., Jost, J.D., Knill, E., Langer, C., Ozeri, R., et al.: Quantum information processing with trapped ions. In: AIP Conference Proceedings, vol. 770, pp. 350–358. AIP (2005)Google Scholar
  2. 2.
    Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)Google Scholar
  3. 3.
    Biamonte, J.D., Allen, J.S., Perkowski, M.A.: Fault models for quantum mechanical switching networks. J. Electron. Test. 26(5), 499–511 (2010)Google Scholar
  4. 4.
    Cormen, T.H.: Introduction to Algorithms. MIT press, Cambridge (2009)Google Scholar
  5. 5.
    Feynman, R.P.: Quantum mechanical computers. Found. Phys. 16(6), 507–531 (1986)Google Scholar
  6. 6.
    Gottesman, D.: Stabilizer codes and quantum error correction (1997). arXiv preprint quant-ph/9705052Google Scholar
  7. 7.
    Grover, L.K.: A fast quantum mechanical algorithm for database search. In: Proceedings of the Twenty-eighth Annual ACM Symposium on Theory of Computing, pp. 212–219. ACM (1996)Google Scholar
  8. 8.
    Knill, E., Laflamme, R., Ashikhmin, A., Barnum, H., Viola, L., Zurek, W.H.: Introduction to quantum error correction (2002). arXiv preprint quant-ph/0207170Google Scholar
  9. 9.
    Knill, E., Laflamme, R., Viola, L.: Theory of quantum error correction for general noise. Phys. Rev. Lett. 84(11), 2525 (2000)Google Scholar
  10. 10.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)Google Scholar
  11. 11.
    Lee, S., Lee, S.-J., Kim, T., Lee, J.-S., Biamonte, J., Perkowski, M.: The cost of quantum gate primitives. J. Mult. Valued Log. Soft Comput. 12 (2006)Google Scholar
  12. 12.
    Li, C., Liu, L., Pang, X.: A dynamic probability fault localization algorithm using digraph. In: 2009 Fifth International Conference on Natural Computation, August 2009, vol. 6, pp. 187–191 (2009)Google Scholar
  13. 13.
    Majumdar, R., Basu, S., Mukhopadhyay, P., Sur-Kolay, S.: Error tracing in linear and concatenated quantum circuits (2016). arXiv preprint arXiv:1612.08044
  14. 14.
    Majumdar, R., Saini, S.: A novel design of reversible 2: 4 decoder. In: 2015 International Conference on Signal Processing and Communication (ICSC), pp. 324–327. IEEE (2015)Google Scholar
  15. 15.
    Mondal, B., Das, P., Pradyut, S., Chakraborty, S.: A comprehensive fault diagnosis technique for reversible logic circuits. Comp. Electr. Eng. 40(7), 2259–2272 (2014)Google Scholar
  16. 16.
    Munro, W.J., Nemoto, K., Spiller, T.P., Barrett, S.D., Kok, P., Beausoleil, R.G.: Efficient optical quantum information processing. J. Opt. B: Quantum Semiclassical Opt. 7(7), S135 (2005)Google Scholar
  17. 17.
    Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge university press, Cambridge (2010)Google Scholar
  18. 18.
    Obenland, K.M., Despain, A.M., Turchette, T.Q.A., Hood, C.J., Lange, W., Mabuchi, H., Kimble, H.J., et al.: Impact of errors on a quantum computer architecture (1996)Google Scholar
  19. 19.
    Peres, Asher: Reversible logic and quantum computers. Phys. Rev. A 32(6), 3266 (1985)MathSciNetCrossRefGoogle Scholar
  20. 20.
    Rahaman, H., Kole, D.K., Das, D.K., Bhattacharya, B.B.: On the detection of missing-gate faults in reversible circuits by a universal test set. In: 21st International Conference on VLSI Design. VLSID 2008. pp. 163–168. IEEE (2008)Google Scholar
  21. 21.
    Saligram, R., Hegde, S.S., Kulkarni, S.A., Bhagyalakshmi, H.R., Venkatesha, M.K.: Design of fault tolerant reversible multiplexer based multi-boolean function generator using parity preserving gates. Int. J. Comput. Appl. 66(19) (2013)Google Scholar
  22. 22.
    Shor, P.W.: Scheme for reducing decoherence in quantum computer memory. Phys. Rev. A 52(4), R2493 (1995)Google Scholar
  23. 23.
    Shor, P.W.: Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer. SIAM Rev. 41(2), 303–332 (1999)Google Scholar
  24. 24.
    Steane, A.M.: Error correcting codes in quantum theory. Phys. Rev. Lett. 77(5), 793 (1996)Google Scholar
  25. 25.
    Strauch, F.W., Johnson, P.R., Dragt, A.J., Lobb, C.J., Anderson, J.R., Wellstood, F.C.: Quantum logic gates for coupled superconducting phase qubits. Physical Rev. Lett. 91(16), 167005 (2003)Google Scholar
  26. 26.
    Surhonne, A.P., Chattopadhyay, A., Wille, R.: Automatic test pattern generation for multiple missing gate faults in reversible circuits. In: International Conference on Reversible Computation, pp. 176–182. Springer (2017)Google Scholar
  27. 27.
    Thapliyal, H., Ranganathan, N.: Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. (JETC) 6(4), 14 (2010)Google Scholar
  28. 28.
    Tommaso, T.: Reversible computing. In: Automata, Languages and Programming, pp. 632–644 (1980)Google Scholar
  29. 29.
    Wille, R., Drechsler, R.: Bdd-based synthesis of reversible logic for large functions. In: Proceedings of the 46th Annual Design Automation Conference, pp. 270–275. ACM (2009)Google Scholar
  30. 30.
    Zamani, M., Farazmand, N., Tahoori, M.B.: Fault masking and diagnosis in reversible circuits. In: 16th IEEE European Test Symposium (ETS), pp. 69–74. IEEE (2011)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Ramyadeep Dey
    • 1
  • Paramita Bandyopadhyay
    • 1
  • Somenath Chandra
    • 1
  • Ritajit Majumdar
    • 2
  1. 1.Department of Computer Science & Engineering, B. P. Poddar Institute of Management & TechnologyMaulana Abul Kalam Azad University of TechnologyKolkataIndia
  2. 2.Advanced Computing & Microelectronics UnitIndian Statistical InstituteKolkataIndia

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