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Taxonomy of Decimal Multiplier Research

  • Diganta Sengupta
  • Mahamuda Sultana
Conference paper
First Online:
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 88)

Abstract

Decimal arithmetic hardware research accelerated in the last decade with introduction of decimal floating point formats in “IEEE 754-2008” standards. During the revision phase (IEEE 754R), 2000–2008, global research on decimal arithmetic witnessed state-of-the-art decimal hardware proposals as well as software routines for decimal computations on general-purpose microprocessors. Multiplication forms a fundamental arithmetic operation and an integral part of arithmetic hardware units. This paper provides taxonomy of the major contributions in decimal multiplier research.

Keywords

Decimal architecture Fixed point multiplier Floating point multiplier Decimal floating point Taxonomy 
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References

  1. 1.
    Schmid, H.: Decimal Computation. Wiley (1974)Google Scholar
  2. 2.
    Richards, R.: Arithmetic Operations in Digital Computers. D. Van Nostrand Company, Inc. (1955)Google Scholar
  3. 3.
    Vazquez, A., Antelo, E., Montuschi, P.: Improved design of high-performance parallel decimal multipliers. IEEE Trans. Comput. 59(5), 679–693 (2010)MathSciNetCrossRefzbMATHGoogle Scholar
  4. 4.
    Erle, M., Hickmann, B., Schulte, M.: Decimal floating-point multiplication. IEEE Trans. Comput. 58(7), 902–916 (2009)Google Scholar
  5. 5.
    Cornea, M., Anderson, C., Harrison, J., Tang, P., Schneider, E., Tsen, C.: A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. In: 18th IEEE Symposium on Computer Arithmetic, 2007. ARITH ‘07, Montepellier, pp. 29–37 (2007)Google Scholar
  6. 6.
    Cornea, M.: Intel® Decimal Floating-Point Math Library. Intel® Corporation (2011)Google Scholar
  7. 7.
    JAVA, Sun Microsystems: Class BigDecimal Documentation. JAVA (1996)Google Scholar
  8. 8.
    Cowlishaw, M.: The decNumber C Library, Version 3.68., IBM (January 2010)Google Scholar
  9. 9.
    Simington, R.: The intel 8087 numerics processor extension. BYTE Mag. 8(4), 154 (1983)Google Scholar
  10. 10.
    Cowlishaw, M.: Decimal floating-point: algorism for computers. In: Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH’03), pp. 104–111 (2003)Google Scholar
  11. 11.
    Erle, M., Schulte, M., Linebarger, J.: Potential speedup using decimal floating-point hardware. In: Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002, Pacific Grove, CA, USA, vol. 2, pp. 1073–1077, Nov 2002Google Scholar
  12. 12.
    Webb, C.: IBM z10: the next-generation mainframe microprocessor. IEEE Micro 28(2), 19–29 (2008)Google Scholar
  13. 13.
    Raafat, R., Abdel-Majeed, A., Samy, R., ElDeeb, T., Farouk, Y., Elkhouly, M., Fahmy, H.: A decimal fully parallel and pipelined floating point multiplier. In: 42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, pp. 1800–1804 (2008)Google Scholar
  14. 14.
    Fahmy, H., ElDeeb, T., Hassan, M.: Decimal floating point for future processors. In: International Conference on Microelectronics (ICM), Cairo, pp. 443–446 (2010)Google Scholar
  15. 15.
    Cowlishaw, M.: Densely packed decimal encoding. Comput. Digit. Techn. 149(3), 102–104 (2002)CrossRefGoogle Scholar
  16. 16.
    IEEE Computer Society: IEEE Standards for Floating-Point Arithmetic 754-2008, IEEE. Aug 2008Google Scholar
  17. 17.
    Quach, N., Takagi, N., Flynn, M.: Systematic IEEE rounding method for high-speed floating-point multipliers. IEEE Trans. Very Larg. Scale Integr. VLSI Syst. 12(5), 511–521 (2004)CrossRefGoogle Scholar
  18. 18.
    Even, G., Seidel, P.: A comparison of three rounding algorithms for IEEE floating-point multiplication. IEEE Trans. Comput. 49(7), 638–650 (2000)CrossRefGoogle Scholar
  19. 19.
    Wang, L.-K., Schulte, M.: Decimal floating-point adder and multifunction unit with injection-based rounding. In: 18th IEEE Symposium on Computer Arithmetic, 2007. ARITH ‘07, Montepellier, pp. 56–68 (2007)Google Scholar
  20. 20.
    Wang, L.-K., Schulte, M., Thompson, J., Jairam, N.: Hardware designs for decimal floating-point addition and related operations. IEEE Trans. Comput. 58(3), 322–335 (2009)MathSciNetCrossRefzbMATHGoogle Scholar
  21. 21.
    Tsen, C., Gonzalez-Navarro, S., Schulte, M., Hickmann, B., Compton, K.: A combined decimal and binary floating-point multiplier. In: 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, Boston, MA, pp. 8–15 (2009)Google Scholar
  22. 22.
    Tsen, C., Schulte, M., Gonzalez-Navarro, S.: Hardware design of a binary integer decimal-based IEEE P754 rounding unit. In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2007, Montreal, Que, pp. 115–121 (2007)Google Scholar
  23. 23.
    Camina, S.: A comparison of taxonomy generation techniques using Bibliometric. EECS Thesis, Massachusetts Institute of technology (2010)Google Scholar
  24. 24.
    Guardia, C.: Implementation of a fully pipelined BCD multiplier in FPGA. In: VIII Southern Conference on Programmable Logic (SPL), 2012, Bento Goncalves, pp. 1–6 (2012)Google Scholar
  25. 25.
    Carlough, S., Schwarz, E.: Decimal Multiplication using Digit Recoding. US, Patent US 7136893 B2, US. 14 Nov 2006Google Scholar
  26. 26.
    Baesler, M., Teufel, T.: FPGA implementation of a decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier. In: International Conference on Reconfigurable Computing and FPGAs 2009, Quintana Roo, pp. 6–11 (2009)Google Scholar
  27. 27.
    Erle, M., Schulte, M.: Decimal multiplication via carry-save addition. In: Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 348–358 (2003)Google Scholar
  28. 28.
    Croy, J.: Improved arrangement of a decimal multiplier. IRE Trans. Electron. Comput. EC-9(2), 263 (1960)Google Scholar
  29. 29.
    Han, L., Ko, S.-B.: High-speed parallel decimal multiplication with redundant internal encodings. IEEE Trans. Comput. 62(5), 956–968 (2013)MathSciNetCrossRefzbMATHGoogle Scholar
  30. 30.
    Castellanos, I., Stine, J.: Decimal partial product generation architectures. In: 51st Midwest Symposium on Circuits and Systems 2008, Knoxville, TN, pp. 962–965 (2008)Google Scholar
  31. 31.
    Bozdas, K., Alkar, A.: Analysis on the column sum boundaries of decimal array multipliers. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) 2012, Boise, ID, pp. 318–321 (2012)Google Scholar
  32. 32.
    Erle, M., Schulte, M., Hickmann, B.: Decimal floating-point multiplication via carry-save addition. In: 18th IEEE Symposium on Computer Arithmetic, 2007. ARITH ‘07, Montepellier, pp. 46–55. June 2007Google Scholar
  33. 33.
    Dadda, L., Nannarelli, A.: A variant of a Radix-10 combinational multiplier. In: IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 3370–3373 (2008)Google Scholar
  34. 34.
    Hickman, B., Krioukov, A., Schulte, M., Erle, M.: A parallel IEEE P754 decimal floating-point multiplier. In: 25th International Conference on Computer Design, 2007. ICCD 2007. Lake Tahoe, CA, pp. 296–303 (2007)Google Scholar
  35. 35.
    Gorgin, S., Jaberipur, G.: Sign-magnitude encoding for efficient VLSI realization of decimal multiplication. IEEE Trans. Very Larg. Scale Integr. (VLSI) Syst. (99), 1–13 (2016)Google Scholar
  36. 36.
    Erle, M., Hickmann, B.: Combined binary/decimal fixed-point multiplier and method. US, Patent US8577952 B2, US. 5 Nov 2013Google Scholar
  37. 37.
    Dadda, L., Pisoni, M., Santambrogio, M.: A parallel-serial decimal multiplier architecture. In: IEEE 15th International Conference on Computational Science and Engineering (CSE), 2012, Nicosia, pp. 310–317 (2012)Google Scholar
  38. 38.
    Hickmann, B., Schulte, M., Erle, M.: Improved combined binary/decimal fixed-point multipliers. In: IEEE International Conference on Computer Design, 2008. ICCD 2008. Lake Tahoe, CA, pp. 87–94 (2008)Google Scholar
  39. 39.
    Gorgin, S., Jaberipur, G.: Fully redundant decimal arithmetic. In: 2009 19th IEEE International Symposium on Computer Arithmetic, pp. 145–152 (2009)Google Scholar
  40. 40.
    Jaberipur, G., Kaivani, A.: Binary-coded decimal digit multipliers. IET Comput. Digit. Tech. 1(4), 377–381 (2007)CrossRefGoogle Scholar
  41. 41.
    Jaberipur, G., Kaivani, A.: Improving the speed of parallel decimal multiplication. IEEE Trans. Comput. 58(11), 1539–1552 (2009)MathSciNetCrossRefzbMATHGoogle Scholar
  42. 42.
    James, R., Jacob, K., Sasi, S.: High performance, low latency double digit decimal multiplier on ASIC and FPGA. In: World Congress on Nature and Biologically Inspired Computing, 2009. NaBIC 2009, Coimbatore, pp. 1445–1450 (2009)Google Scholar
  43. 43.
    James, R., Shahana, T., Jacob, K., Sasi, S.: Decimal multiplication using compact BCD multiplier. In: Electronic Design, 2008. ICED 2008. penang, pp. 1–6. Dec 2008Google Scholar
  44. 44.
    James, R., Shahana, T., Jacob, P., Sasi, S.: Fixed point decimal multiplication using RPS algorithm. In: IEEE International Symposium on Parallel and Distributed Processing with Applications 2008, Sydney, NSW, pp. 343–350 (2008)Google Scholar
  45. 45.
    Kaivani, A., Han, L., Ko, S.-B.: Improved design of high-frequency sequential decimal multipliers. Electron. Lett. Inst. Eng. Technol. 50(7), 558–560 (2014)Google Scholar
  46. 46.
    Kenney, R., Schulte, M., Erle, M.: A high-frequency decimal multiplier. In: Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004, pp. 26–29 (2004)Google Scholar
  47. 47.
    Lin, K., Chiu, Y., Lin, T.-H.: A decimal squarer with efficient partial product generation. In: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip 2010, Madrid, pp. 213–218 (2010)Google Scholar
  48. 48.
    Navarro, S., Tsen, C., Schulte, M.: Binary integer decimal-based floating-point multiplication. IEEE Trans. Comput. 62(7), 1460–1466 (2013)MathSciNetCrossRefzbMATHGoogle Scholar
  49. 49.
    Ohtsuki, T., Oshima, Y., Ishikawa, S., Yabe, H., Fukuta, M.: Apparatus for decimal multiplication. US, Patent US 4677583 A, US. 30 June 1987Google Scholar
  50. 50.
    Osama, D., Khaleel, A., Tulic, N., Mhaidat, K.: FPGA implementation of binary coded decimal digit adders and multipliers. In: 8th International Symposium on Mechatronics and its Applications (ISMA), 2012, Sharjah, pp. 1–5 (2012)Google Scholar
  51. 51.
    Sutter, G., Todorovich, E., Bioul, G., Vazquez, M., Deschamps, J.: FPGA implementations of BCD multipliers. In: International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig ‘09. Quintana Roo, pp. 36–41 (2009)Google Scholar
  52. 52.
    Ueda, T.: Decimal multiplying assembly and multiply module. US, Patent US 5379245, US. Jan 1995Google Scholar
  53. 53.
    Vázquez, Á., Antelo, E., Bruguera, J.: Fast Radix-10 multiplication using redundant BCD codes. IEEE Trans. Comput. 63(8), 1902–1914 (2014)MathSciNetCrossRefzbMATHGoogle Scholar
  54. 54.
    Veeramachaneni, S., Srinivas, M.: Novel high-speed architecture for 32-Bit binary coded decimal (BCD) multiplier. In: 2008 International Symposium on Communications and Information Technologies, 2008. ISCIT, Lao, pp. 543–546 (2008)Google Scholar
  55. 55.
    Véstias, M., Neto, H.: Iterative decimal multiplication using binary arithmetic. In: 2011 VII Southern Conference on VII Southern Conference on Programmable Logic (SPL). Cordoba, pp. 257–262 (2011)Google Scholar
  56. 56.
    Véstias, M., Neto, H.: Parallel decimal multipliers and squarers using Karatsuba-Ofman’s algorithm. In: 15th Euromicro Conference on Digital System Design (DSD), 2012, Izmir, pp. 782–788 (2012)Google Scholar
  57. 57.
    Véstias, M., Neto, H.: Parallel decimal multipliers using binary multipliers. In: VI Southern Programmable Logic Conference (SPL), 2010, Ipojuca, pp. 73–78 (2010)Google Scholar
  58. 58.
    Wahba, A., Fahmy, H.: Area efficient and fast combined binary/decimal floating point fused multiply add unit. IEEE Trans. Comput. (99), 1 (2016)Google Scholar
  59. 59.
    Zhu, M., Baker, A., Jiang, Y.: On a parallel decimal multiplier based on hybrid 8421–5421 BCD recoding. In: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, pp. 1391–1394 (2013)Google Scholar
  60. 60.
    Zhu, M., Jiang, Y.: An area-time efficient architecture for 16 × 16 decimal multiplications. In: Tenth International Conference on Information Technology: New Generations (ITNG), 2013, Las Vegas, NV, pp. 210–216 (2013)Google Scholar
  61. 61.
    Baesler, M., Voigt, S.-O., Teufel, T.: A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a virtex-5 FPGA. Int. J. Reconfigurable Comput. 2010, 13 (2010). (Article ID 357839)Google Scholar
  62. 62.
    Cui, X., Liu, W., Wenwen, D., Lombardi, F.: A parallel decimal multiplier using hybrid binary coded decimal (BCD) codes. In: IEEE 23nd Symposium on Computer Arithmetic (ARITH) 2016 (2016)Google Scholar
  63. 63.
    Varma, C., Ahmed, S., Srinivas, M.: A decimal/binary multi-operand adder using a fast binary to decimal converter. In: 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (2014)Google Scholar
  64. 64.
    Eduardo, C., Guardia, M.: Implementation of a fully pipelined BCD multiplier in FPGA. In: VIII Southern Conference on Programmable Logic (SPL) (2012)Google Scholar
  65. 65.
    Ding, H., Shu, P., Wang, X., Yang, J.: A design and implementation of decimal floating-point multiplication unit based on SOPC. In: Third International Conference on Digital Manufacturing and Automation (ICDMA) (2012)Google Scholar
  66. 66.
    Tsen, S., Gonzalez-Navarro, S., Schulte, M., Compton, K.: Hardware designs for binary integer decimal-based rounding. IEEE Trans. Comput. 60(5), 614–627 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
  67. 67.
    Vázquez, Á., Dinechin, F.: Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. In: International Conference on Field-Programmable Technology (FPT) (2010)Google Scholar
  68. 68.
    Navarro, S., Tsen, C., Schulte, M.: A binary integer decimal-based multiplier for decimal floating-point arithmetic. In: Forty-First Asilomar Conference on Signals, Systems and Computers, 2007. ACSSC 2007 (2007)Google Scholar
  69. 69.
    Rekha, K., Jacob, K., Sasi, S.: Performance analysis of double digit decimal multiplier on various FPGA logic families. In: 5th Southern Conference on Programmable Logic, 2009. SPL. Sao Carlos, pp. 165–170 (2009)Google Scholar
  70. 70.
    Minchola, C., Sutter, G.: A FPGA IEEE-754-2008 Decimal64 floating-point multiplier. In: International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig ‘09. Quintana Roo, pp. 59–64 (2009)Google Scholar
  71. 71.
    Kaivani, A., Chen, L., Ko, S.: High-frequency sequential decimal multipliers. In: 2012 IEEE International Symposium on Circuits and Systems (ISCAS). Seoul, pp. 3045–3048 (2012)Google Scholar
  72. 72.
    Lang, T., Nannarelli, A.: A Radix-10 combinational multiplier. In: Fortieth Asilomar Conference on Signals, Systems and Computers, 2006. ACSSC ‘06. Pacific Grove, CA, pp. 313–317 (2006)Google Scholar
  73. 73.
    Gorgin, S., Jaberipur, G., Parhami, B.: Design and evaluation of decimal array multipliers. In: 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers, pp. 1782–1786. IEEE. Nov 2009Google Scholar
  74. 74.
    Neto, H., Vestias, M.: Decimal multiplier on FPGA using embedded binary multipliers. In: 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, pp. 197–202 (2008)Google Scholar
  75. 75.
    Gonzalez-Navarro, S., Tsen, C., Schulte, M.: A binary integer decimal-based multiplier for decimal floating-point arithmetic. In: 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, pp. 353–357 (2007)Google Scholar
  76. 76.
    Baesler, M., Voigt, S.-O., Teufel, T.: An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplier. In: 2010 International Conference on Field Programmable Logic and Applications (FPL). Milano, pp. 489–495 (2010)Google Scholar
  77. 77.
    Erle, M., Schwarz, E., Schulte, M.: Decimal multiplication with efficient partial product generation. In: 17th IEEE Symposium on Computer Arithmetic, 2005. ARITH-17 2005, pp. 21–28 (2005)Google Scholar
  78. 78.
    Jouppi, N.: Wallace-tree multipliers using half and full adders. US, Patent US 6065033 A, US. 16 May 2000Google Scholar
  79. 79.
    Lehman, M.: Short-cut multiplication and division in automatic binary digital computers, with special reference to a new multiplication process. Proc. IEEE—Part B: Radio Electron. Eng. 105(23), 496–504 (2010)Google Scholar

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© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Techno India-BatanagarKolkataIndia
  2. 2.Techno India College of TechnologyKolkataIndia

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