Abstract
Adders are the integral part of arithmetic logic units in digital system. Performance of the adder circuits decides the performance of those circuit and systems. Full adders are designed either in conventional approach or hybrid approach. In conventional approach, only one logic style is used, whereas in hybrid approach, two or more logic styles are used. A performance analysis between conventional and hybrid 1-bit full adder circuits is presented in this paper. In conventional design, complementary metal–oxide–semiconductor (CMOS) full adder, complementary pass logic (CPL) full adder, and transmission gate full adder (TGA) are the most popular. In this paper, CMOS full adder and CPL full adder are reported. The hybrid adder reported in this paper is designed using CMOS logic and transmission gate (TG) logic. The circuits are implemented using Cadence virtuoso tools with 180 nm United Microelectronics Company (UMC) technology. From the pre-layout simulation, performance metrics such as power, speed, and power delay products were computed. Performance of each of the circuits in terms of power, speed, power delay product (PDP), and area requirements in terms of transistor counts for the design is then compared.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
D. Radhakrishnan,: Low-voltage low-power CMOS full adder. IEEE Proc. -Circuits Devices Syst., vol. 148, no. 1, pp. 19–24, (2001).
N. H. E. Weste, D. Harris, and A. Banerjee.: CMOS VLSI Design: A Circuits and Systems Perspective. 3rd ed. Delhi, India: Pearson Education, (2006).
C. H. Chang, J. M. Gu, and M. Zhang.: A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, (2005).
J. M. Rabaey, A. Chandrakasan, and B. Nikolic.: Digital Integrated Circuits: A Design Perspective, 2nd ed. Delhi, India: Pearson Education, (2003).
R. Zimmermann and W. Fichtner.: Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, (1997).
K. Chu and D. Pulfrey.: A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic. IEEE J. Solid-State Circuits, vol. 22, pp. 528–532, (1987).
J. H. Pasternak and C. A. T. Salama.: Differential pass-transistor logic. IEEE Circuits & Devices, pp. 23–28, (1993).
A. M. Shams, T. K. Darwish, and M. A. Bayoumi.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, (2002).
M. Vesterbacka.: A 14-transistor CMOS full adder with full voltage swing nodes. Proc. IEEE Workshop Signal Process. Syst. (SiPS), pp. 713–722, (1999).
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, and A. Dandapat.: Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Trans. Very Large Scale Integr. Syst., vol. 23, no. 10, pp. 2001–2008, (2015).
I. Hassoune, D. Flandre, I. O’Connor, and J. Legat.: ULPFA: A new efficient design of a power-aware full adder. IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 2066–2074, (2010).
J.-M. Wang, S.-C. Fang, and W.-S. Feng.: New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid-State Circuits, vol. 29, pp. 780–786, (1994).
P. Ng, P. T. Balsara, and D. Steiss.: Performance of CMOS differential circuits. IEEE J. Solid-State Circuits, vol. 31, pp. 841–846, (1996).
J.-M. Wang, S.-C. Fang, and W.-S. Feng.: New efficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits, vol. 29, pp. 780–786, (1994).
H. T. Bui, Y. Wang, and Y. Jiang.: Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 25–30, (2002).
I. Hussain and M. Kumar.: Design and performance analysis of a 3-2 compressor by using improved architecture. Journal of Active and Passive Electronic Devices, vol. 12, no. 3–4, pp. 173–181, (2017).
Acknowledgements
The authors would like to thank VLSI Laboratory, Department of Electronics and Communication Engineering, NIT Silchar, for providing the simulation facility.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Hussain, I., Chaudhury, S. (2018). Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits. In: Bera, R., Sarkar, S., Chakraborty, S. (eds) Advances in Communication, Devices and Networking. Lecture Notes in Electrical Engineering, vol 462. Springer, Singapore. https://doi.org/10.1007/978-981-10-7901-6_6
Download citation
DOI: https://doi.org/10.1007/978-981-10-7901-6_6
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7900-9
Online ISBN: 978-981-10-7901-6
eBook Packages: EngineeringEngineering (R0)