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Developing High-Performance AVM Based VLSI Computing Systems: A Study

  • Siba Kumar Panda
  • Dhruba Charan Panda
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 710)

Abstract

With the initiation of ancient Vedic mathematics (AVM) concepts, very large-scale integration technique becomes more powerful in developing various VLSI computing systems. In the last decade, people have tried to integrate the Vedic mathematics techniques with the VLSI theory. Hence, analyzing methods, designing and manipulating the performance from circuit- and system-level perspectives become a vital task and challenging too. Performance study of various diverse techniques that are used for developing high-performance VLSI computing systems is the central focus of this paper. This paper provides a comprehensive survey of different designing techniques, complementing the limits of existing reviews in the literature. The survey covers introduction to Vedic methods, motivation toward the work, various designing techniques with their limitations, etc. This paper can be seen as a foremost step to present a state-of-the-art impression of revision work carried in developing high-performance VLSI computing systems.

Keywords

VLSI computing VLSI signal processing AVM FPGA HDL 

Notes

Acknowledgements

All the studies are carried out at Centurion University of Technology and Management, Odisha, India. The authors also express their sincere gratitude to Centurion University of Technology & Management, Jatni, Bhubaneswar, Odisha for providing a high-end research platform.

References

  1. 1.
    Parhami, B.: Computer arithmetic: algorithms and hardware designs, 2nd edn., Oxford University Press (2010)Google Scholar
  2. 2.
    Maharaja, J.S.S.B.K.T.: Vedic mathematics: Motilal Banarsidass Publishers Pvt. Ltd, Delhi (2007)Google Scholar
  3. 3.
    Sharma, P., Singh, R.P., Singh, R., Pande, P.: Design of Quadratic Equations Multiplier (for up to 2-Bit Number) Using Vedic Technique. In: Proceeding of International Conference on Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 479. Springer, Singapore (2017)Google Scholar
  4. 4.
    Barik, R.K., Pradhan, M.: Efficient ASIC and FPGA implementation of cube architecture. IET Computers & Digital Techniques vol. 11(1), pp. 43–49 (2017)Google Scholar
  5. 5.
    Panda, S.K., Jena, A.: FPGA-VHDL implementation of pipelined square root circuit for VLSI signal processing applications. International journal of computer application, vol. 142, pp. 20–24 (2016)Google Scholar
  6. 6.
    Bansal, Y., Charu, M.: A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders, Computer. Electr. Eng., 49, pp. 39–49. Comput. Electr. Eng. (2016)Google Scholar
  7. 7.
    Srimani, S., Kundu, D.K., Panda, S., Maji, B.: Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra. In Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 335. Springer, New Delhi (2015)Google Scholar
  8. 8.
    Anjana, S., Pradeep, C., Samuel, P.: Synthesize of high speed floating-point multipliers based on Vedic mathematics. Procedia Computer Science, vol. 46, pp. 1294–1302, December 2015Google Scholar
  9. 9.
    Barik, R.K., Pradhan, M.: Area-time efficient square architecture (Advances Series D, AMSE Press), vol. 20, no. 1, pp. 21–35 (2015)Google Scholar
  10. 10.
    Panda, S.K., Sahu, A.: A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications. International journal of computer application, vol. 120, pp. 31–36 (2015)Google Scholar
  11. 11.
    Khan, A., Das, R.: Novel Approach of Multiplier Design Using Ancient Vedic Mathematics. In Information Systems Design and Intelligent Applications. Advances in Intelligent Systems and Computing, vol 340, pp 265–272, Springer, New Delhi (2015)Google Scholar
  12. 12.
    Sethi, K., Panda, R.: Multiplier less high-speed squaring circuit for binary numbers. International journal of electronics, vol. 102, pp. 433–443. Taylor Francis (2014)Google Scholar
  13. 13.
    Saha, P., Kumar, D., Bhattacharyya, P., et al: Vedic division methodology for high-speed very large scale integration application, J. Eng., 1, (1), pp. 1–9. (2014)Google Scholar
  14. 14.
    Saha, P., et al.: Improved matrix multiplier design for high speed signal processing applications. IET Circuits Devices and Syst. 8(1), pp. 27–37 (2014)Google Scholar
  15. 15.
    Rahman, A., Al-Kafi, A.: New efficient hardware design methodology for modified non-restoring square root algorithm. In: International conference on informatics electronics and Vision, pp. 1–6. Dhaka (2014)Google Scholar
  16. 16.
    Pradhan, M., Panda, R.: High speed multiplier using Nikhilam sutra algorithm of Vedic mathematics, Int. J. Electron., 101, (3), pp. 300–307 (2014)Google Scholar
  17. 17.
    Poornima, M., et al.: Implementation of multiplier using Vedic algorithm. IJITEE 2(6), pp. 219–223 (2013)Google Scholar
  18. 18.
    Saravanan, P., Chandrasekar, P., Chandran, L., Sriram, N., Kalpana, P. Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic. In: Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg (2012)Google Scholar
  19. 19.
    Senthilpari, B.C., Kavitha, S.: Proposed low power, high speed, adder-based, 65 nm square root circuit. Journal of Microelectronics, vol. 42, pp. 445–451. Elsevier Science (2011)Google Scholar
  20. 20.
    Sajid, I., Ahmed, M.: Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm. In: 2nd International conference on computer and automation engineering, pp. 226–230. IEEE press, Islamabad (2011)Google Scholar
  21. 21.
    Saha, P., et al.: ASIC design of a high speed low power circuit for factorial calculation using ancient vedic mathematics, Microelectronics. J. 42, pp. 1343–1352 (2011)Google Scholar
  22. 22.
    Sutikno, T.: An efficient implementation of non-restoring square root algorithm in gate level. International journal of computer theory and engineering, vol. 3, pp. 46–51(2011)Google Scholar
  23. 23.
    Sultana, S., Radecka, K.: Reversible implementation of square-root circuit. In: 18th IEEE international conference on electronic circuits and systems, pp. 141–144. IEEE Press, Canada (2011)Google Scholar
  24. 24.
    Kasliwal, P.S., Patil, B., Gautam, D.: Performance evaluation of squaring operation by Vedic mathematics, IETE J. Res., 57, (1), pp. 39–41 (2011)Google Scholar
  25. 25.
    Sutikno, T., Zakwan, A.: A simple strategy to solve complicated square root problem in DTC for FPGA implementation. In: IEEE symposium on industrial electronics and application, pp. 691–695. IEEE press, Penang (2010)Google Scholar
  26. 26.
    Deshpande, A., Draper, J.: Squaring units and a comparison with multipliers. Proc. of 53th Int. Symp. on Circuits and Systems, pp. 1266–1269(2010)Google Scholar
  27. 27.
    Chakrabarty, S.M., Kolluru, R.: Enjoy vedic mathematics. The Art of Living (Diamond Books), 31 Oct 2010Google Scholar
  28. 28.
    Ashenden, P.J.: The designer’s guide to VHDL. Morgan Kaufmann (2010)Google Scholar
  29. 29.
    Ramalatha, M., Thanushkodi, K., Deena Dayalan, K., et al: A novel time and energy efficient cubing circuit using Vedic mathematics for finite field arithmetic. Proc. of 09th Int. Conf. on Advances in Recent Technologies in Communication and Computing, pp. 873–875(2009)Google Scholar
  30. 30.
    Meheta, P., Gawali, D.: Conventional versus vedic mathematical method for hardware implementation of a multiplier. In: Proceedings of IEEE International Conferences on Advances in Computing, Control and Telecommunication, pp. 640–642, Trivandrum, Kerala (2009)Google Scholar
  31. 31.
    Pedroni, V. A.: Circuit design with VHDL. Cambridge, MA: The MIT Press (2008)Google Scholar
  32. 32.
    Samavi, S., Sadrabadi, A., Fanian, A.: Modular array structure of non-restoring square root circuit. Journal of system architecture, vol. 54, pp. 957–966. Elsevier Science (2008)Google Scholar
  33. 33.
    Wang, L., Schulte, M.: Decimal floating point square root using Newton-Raphson iteration. In: 16th International conference on application specific systems architecture processors, pp. 309–315. IEEE press, USA (2005)Google Scholar
  34. 34.
    Thapliyal, H., Kotiyal, S., Srinivas, M.: Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics. Proc. of 48th Int. Symp. on Circuits and Systems, pp. 1462–1465(2005)Google Scholar
  35. 35.
    Chidgupkar, P. D., Karad, M.T.: The implementation of Vedic algorithms in digital signal processing. Glob. J. Eng. Educ., 8(2), pp. 153–158 (2004)Google Scholar
  36. 36.
    Thapliyal, H., Arbania, H.R.: A time-area-power efficient multiplier and square architecture based on ancient indian vedic mathematics. In: Proceedings of the 2004 International Conference on VLSI (VLSI ’04), Las Vegas, Nevada, pp. 434–439, June (2004)Google Scholar
  37. 37.
    Palnitkar, S.: Verilog HDL: A guide to digital design and synthesis. Prentice Hall Professional (2003)Google Scholar
  38. 38.
    Ercegovac, M.D., Lang, T., Muller, J.M., et al: Reciprocation, square root, inverse square root, and some elementary functions using small multipliers. IEEE Trans. Comput., 49(7), pp. 628–637 (2000)Google Scholar
  39. 39.
    Liddicoat, A.A., Flynn, M.: Parallel square and cube computations. Proc. of 34th Int. Conf. on Signals, Systems and Computers, vol. 2, pp. 1325–1329 (2000)Google Scholar
  40. 40.
    Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, London (1999)Google Scholar
  41. 41.
    Li, Y., Chu, W.: Implementation of single precision floating point square root on FPGAs. In: 5th IEEE symposium on FPGA for custom computing machines, pp. 226–232. California, USA (1997)Google Scholar
  42. 42.
    Li, Y., Chu, W.: Parallel array implementations of non-restoring square root algorithm. In: International conference on computer design, pp. 690–695. IEEE press, USA (1997)Google Scholar
  43. 43.
    Guenther, H.: Arithmetic operations of the machine fundamentals of digital machine computing, Springer publication (1996)Google Scholar
  44. 44.
    Li, Y., Chu, W.: A new non-restoring square root algorithm and its VLSI implementation. In: IEEE International Conference on computer design, pp. 539–544. Texas, USA (1996)Google Scholar
  45. 45.
    O’Leary, J., Leeser, M.: Non-restoring integer square root-A case study in design by principled optimization. Technical report, Cornell University (1994)Google Scholar
  46. 46.
    Morris Mano, M.: Computer System Architecture, 3rd edn, pp. 346–348. Prentice-Hall, New Jersey (1993)Google Scholar
  47. 47.
    Jeganathan Sriskandarajah: Secrets of ancient maths: vedic mathematics. Journal of Indic Studies Foundation, CaliforniaGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of ECECenturion University of Technology & ManagementJatniIndia
  2. 2.P. G. Department of Electronic ScienceBerhampur UniversityBerhampurIndia

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