Abstract
A radiation-tolerant phase-locked loop (PLL) is designed in 65 nm CMOS technology. A double feedback loop self-sampling structure is proposed to improve the anti-radiation capability. A High matched current-based charge pump is hardened by using sensitive nodes compression and transformation technology. The simulation results show that the proposed PLL has no significant variations under heavy-ion and it could output good jitter signals with high frequency.
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Acknowledgments
This research was supported by National Natural Science Foundation of China Program (No. 61504169).
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Yuan, H., Chen, J., Liang, B., Guo, Y. (2018). A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2017. Communications in Computer and Information Science, vol 600. Springer, Singapore. https://doi.org/10.1007/978-981-10-7844-6_5
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DOI: https://doi.org/10.1007/978-981-10-7844-6_5
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