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A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS

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Computer Engineering and Technology (NCCET 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 600))

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Abstract

Based on 40 nm standard CMOS process, this paper proposes an easy realized, programmable pre-emphasis transmitter. The circuit is used in high performance SerDes (Serializer-Deserializer) chip, which utilizes a 2-tap current-mode pre-emphasis technique, resulting less design complicacy as well as low noise. Furthermore, a tail current DAC enables equalization to be configurable in order to adapt to various data rate condition. Simulation results show 0–6 db pre-emphasis ability and 0–1.3 V differential output voltage swing under 2.5–6.25 GB/s transmission rate, which meet specifications of high speed serial link standards such as PCIE2.1 and RapidIO2.2.

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Acknowledgment

This paper is supported by the research of shared memory architecture for a general purpose microprocessor (No. 61472432).

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Correspondence to Sheng Liu .

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Tan, H., Chen, H., Liu, S., Ma, X., Chi, Y. (2018). A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2017. Communications in Computer and Information Science, vol 600. Springer, Singapore. https://doi.org/10.1007/978-981-10-7844-6_4

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  • DOI: https://doi.org/10.1007/978-981-10-7844-6_4

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7843-9

  • Online ISBN: 978-981-10-7844-6

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