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Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K

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Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 695))

Abstract

The source and drain engineering on dual-metal dual-gate (DMDG)-based 50 nm SOI MOSFET for various high-k gate oxides has been investigated in this work to improve its electrical performance. The proposed structure is designed by modifying source and drain (MSMD) side, and its performance is evaluated on ATLAS device simulator. The effect of this heterogeneous doping on source and drain side of the DMDG transistor led to the reduction of leakage current, decreases DIBL effectively, and improves ION current, thereby enabling the proposed device appropriate for low-power digital applications.

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References

  1. Venkateshwar Reddy, G., Jagadesh Kumar, M.: A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. Nanotechnol. 4(2), 260–268 (2005)

    Article  Google Scholar 

  2. Mishra, V.K., Chauhan, R.K.: Performance analysis of modified source and TDBC based fully-depleted SOI MOSFET for low power digital applications. J. Nanoelectron. Am. Sci. Publ. 12(1), 59–66 (2017)

    Article  Google Scholar 

  3. Mishra, V.K., Chauhan, R.K.: Performance analysis of modified source and TDBC based fully-depleted SOI MOSFET for low power digital applications. J. Nanoelectron. Optoelectron. Am. Sci. Publ. 12(1), 59–66 (2017)

    Article  Google Scholar 

  4. Tripathi, S., Mishra, V.K., Chauhan, R.K.: Performance analysis of dual metal gate modified source fully depleted SOI MOSFET in i-manager’s. J. Embed. Syst. 5(2), 07–12 (2016)

    Google Scholar 

  5. Colinge, J.P., Gao, M.H., Rodriguez, A.R., Claeys, C.: Silicon-on insulator gate-all around device. In: Int. Electron Devices Meeting Tech. Dig., pp. 595–598 (1990)

    Google Scholar 

  6. Long, W., Chin, K.K.: Dual material gate field effect transistor (DMGFET). IEDM Tech. Dig., pp. 549–552 (1997)

    Google Scholar 

  7. Long, W., Ou, H., Kuo, J.-M., Chin, K.K.: Dual material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 46, 865–870 (1999)

    Article  Google Scholar 

  8. Zhou, X., Long, W.: A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology. IEEE Trans. Electron Devices 45, 2546–2548 (1998)

    Article  Google Scholar 

  9. Zhou, X.: Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering. IEEE Trans. Electron Devices 47(1), 113–120 (2000)

    Article  Google Scholar 

  10. Cheng, K.G., Khakifirooz, A.: Fully depleted SOI (FD SOI) technology. Sci China Inf Sci 59, 1–15 (2016)

    Article  Google Scholar 

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Correspondence to Himanshu Yadav .

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Yadav, H., Chauhan, R.K. (2018). Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K. In: Bhateja, V., Coello Coello, C., Satapathy, S., Pattnaik, P. (eds) Intelligent Engineering Informatics. Advances in Intelligent Systems and Computing, vol 695. Springer, Singapore. https://doi.org/10.1007/978-981-10-7566-7_53

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  • DOI: https://doi.org/10.1007/978-981-10-7566-7_53

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7565-0

  • Online ISBN: 978-981-10-7566-7

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