Implementation of High-Performance Floating Point Divider Using Pipeline Architecture on FPGA
Data intensive DSP algorithms mostly depend on double precision (DP) floating point arithmetic operations. With advanced FPGA devices, applications need more floating point arithmetic operations to accelerate reconfigurable logic. Important and complex applications heavily depend on the floating point divider (FPD) blocks. This paper illustrates implementation of low-latency dividers based on pipelining, which is operated at 30% faster than existing divider. DPFPD implemented using field programmable gate array (FPGA) outperforms other ULP dividers. Pipelining architecture of FPD increases the throughput and reduces the power considerably. The architecture is validated for standalone as well as integrated application levels.
KeywordsULP Reconfigurable logic DPFPD FPGA
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