Distributed Lock Relation for Scalable-Delay-Insensitive Circuit Implementation Based on Signal Transition Graph Specification

  • Pitchayapatchaya Srikram
  • Arthit Thongtak
Conference paper


Signal transition graph specification has a potential to describe behavior of hardware system in term of concurrent, sequential and one instance of the same events. One typical idea is for asynchronous control circuits, which is a variety of delay assumption design by means of signal transition graph specification. This paper proposes a distributed lock relation to determine the completion path for multiple-cycle signals. We select the tardy internal-completion signal to be the volunteer signal based on Scalable-Delay-Insensitive (SDI) model. The effectiveness of the proposed methodology is evaluated by cost of area, which is number of internal input signals and literal logic gates.


Asynchronous control circuit Asynchronous logic synthesis Lock relation Multiple-cycle signal Scalable-insensitive delay model Signal transition graphs 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Rajamangala University of Technology ThunyaburiPathumthaniThailand
  2. 2.Chulalongkorn UniversityBangkokThailand

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