Abstract
Signal transition graph specification has a potential to describe behavior of hardware system in term of concurrent, sequential and one instance of the same events. One typical idea is for asynchronous control circuits, which is a variety of delay assumption design by means of signal transition graph specification. This paper proposes a distributed lock relation to determine the completion path for multiple-cycle signals. We select the tardy internal-completion signal to be the volunteer signal based on Scalable-Delay-Insensitive (SDI) model. The effectiveness of the proposed methodology is evaluated by cost of area, which is number of internal input signals and literal logic gates.
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Srikram, P., Thongtak, A. (2018). Distributed Lock Relation for Scalable-Delay-Insensitive Circuit Implementation Based on Signal Transition Graph Specification. In: Ao, SI., Kim, H., Castillo, O., Chan, AS., Katagiri, H. (eds) Transactions on Engineering Technologies. IMECS 2017. Springer, Singapore. https://doi.org/10.1007/978-981-10-7488-2_14
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DOI: https://doi.org/10.1007/978-981-10-7488-2_14
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